AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Document Table of Contents

Disable Ref Clock Sharing

When you set the parameter SHARED_REFCLK_EN to 0, this will disable the ref clock sharing and N set of pll_ref_clk_10g, pll_ref_clk_1g, cdr_ref_clk_10g and cdr_ref_clk_1g are needed, where N=number of channels. These ref clock signals will be connected to their individual channel respectively.