AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Document Table of Contents

Channel Level Reset Scheme

The following diagram shows the reset scheme per channel. mm_reset is used to reset the registers in MAC, PHY, TOD, MDIO and address decoder block, while datapath_reset is used to reset MAC, PHY reset controller and TOD. However, mm_reset and datapath_reset are tied together at multi-channel level in the design example, therefore it is not possible to trigger them separately.

Reset scheme at altera_eth_channel_1588