AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

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ID 683343
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY x
Features Requirements Design Example Walkthrough Components Parameters Design Example Testbench Clocking Scheme Reset Scheme Interface Signals Register Map Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Design Example Walkthrough x
Setting Up the Design Examples Changing Number of Channels Configuring PHY Speed IP Regeneration
Configuring PHY Speed x
Changing Speed between 10G and 1G in 1000BaseX mode Changing Speed between 1G, 100M, and 10M SGMII
Design Example Testbench x
Testbench Components Testbench Files Simulating Testbench Test Case
Simulating Testbench x
Using ModelSim Simulator Using VCS Simulator
Test Case x
Test Scenario for Design Example without IEEE 1588v2 Test Scenario for Design Example with IEEE 1588v2
Clocking Scheme x
Clocking Diagram Sync-E Support
Sync-E Support x
Enable Ref Clock Sharing Disable Ref Clock Sharing
Reset Scheme x
Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Design Example without IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Design Example with IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals MDIO Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals
Register Map x
Master TOD 1G TOD 10G TOD PHY 1G/10G MAC
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

Packet Classifier Interface Signals

The following table lists the packet classifier interface signals. These interface signals are only applicable to design examples with IEEE 1588v2.

Table 12.  Packet Classifier Interface Signals
Signal Direction Width Description
tx_egress_timestamp_request_in_valid[] input [NUM_CHANNELS] Assert this signal to request timestamping for the TX frame. This signal must be asserted in the same clock cycle avalon_st_tx_startofpacket is asserted.
tx_egress_timestamp_request_in_fingerprint[][] input [NUM_CHANNELS][TSTAMP_FP_WIDTH] Use this bus to specify the fingerprint that validates the timestamp for the incoming packet.
clock_operation_mode_mode[][] input [NUM_CHANNELS][2] Determines the clock mode.
  • 00: Ordinary clock
  • 01: Boundary clock
  • 10: End to end transparent clock
  • 11: Peer to peer transparent clock
pkt_with_crc_mode[] input [NUM_CHANNELS] Indicates whether or not a packet contains CRC.
  • 0: Packet contains CRC
  • 1: Packet does not contain CRC
tx_ingress_timestamp_valid[] input [NUM_CHANNELS] Indicates the update for residence time.
  • 0: Prevents update for residence time
  • 1: Allows update for residence time based on decoded results

When this signal is deasserted, tx_etstamp_ins_ctrl_out_residence_ti me_update also gets deasserted.

tx_ingress_timestamp_96b_data[][] input [NUM_CHANNELS][96] 96-bit format of ingress timestamp that holds data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_64b_data[][] input [NUM_CHANNELS][64] 64-bit format of ingress timestamp that holds data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_format[] input [NUM_CHANNELS] The format of the timestamp for calculating the residence time.
  • 0: 96 bits
  • 1: 64 bits

This signal must be aligned to the start of an incoming packet.

Level Two Title