AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

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ID 683343
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY x
Features Requirements Design Example Walkthrough Components Parameters Design Example Testbench Clocking Scheme Reset Scheme Interface Signals Register Map Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Design Example Walkthrough x
Setting Up the Design Examples Changing Number of Channels Configuring PHY Speed IP Regeneration
Configuring PHY Speed x
Changing Speed between 10G and 1G in 1000BaseX mode Changing Speed between 1G, 100M, and 10M SGMII
Design Example Testbench x
Testbench Components Testbench Files Simulating Testbench Test Case
Simulating Testbench x
Using ModelSim Simulator Using VCS Simulator
Test Case x
Test Scenario for Design Example without IEEE 1588v2 Test Scenario for Design Example with IEEE 1588v2
Clocking Scheme x
Clocking Diagram Sync-E Support
Sync-E Support x
Enable Ref Clock Sharing Disable Ref Clock Sharing
Reset Scheme x
Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Design Example without IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Design Example with IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals MDIO Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals
Register Map x
Master TOD 1G TOD 10G TOD PHY 1G/10G MAC
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

Parameters

Table 5.   Parameters for Design Example Customization
Parameter Description Default Value
NUM_CHANNELS Specify the number of channels of 1-Gbps Ethernet(GbE)/10GbE that will be instantiated in the design example. Range from 1 to 12. 2
MDIO_MDC_CLOCK_DIVISOR Use this parameter to set the management data input/output (MDIO) clock divisor. Range from 8 to 64. 32
SHARED_REFCLK_EN Use this parameter to enable the sharing of reference clock refclk between all channels.
  • 0 : disable sharing
  • 1 : enable sharing
1
FIFO_OPTIONS Use this parameter to enable the FIFO in between user Avalon-ST and MAC interface.
  • 0: disable FIFO
  • 1: enable SC FIFO
  • 2: enable DC FIFO
  • 3: enable SC + DC FIFO
Note:

This parameter is available only for design example without IEEE 1588v2.

1
TSTAMP_FP_WIDTH Use this parameter to set the timestamp fingerprint width which follows the setting in 1G/10GbE MAC. You must regenerate the MAC IP if this parameter is changed. Enter the new width value in MAC IP regeneration page.
Note:

This parameter is available only for design example with IEEE 1588v2.

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