AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Public
Document Table of Contents

Parameters

Table 5.   Parameters for Design Example Customization
Parameter Description Default Value
NUM_CHANNELS Specify the number of channels of 1-Gbps Ethernet(GbE)/10GbE that will be instantiated in the design example. Range from 1 to 12. 2
MDIO_MDC_CLOCK_DIVISOR Use this parameter to set the management data input/output (MDIO) clock divisor. Range from 8 to 64. 32
SHARED_REFCLK_EN Use this parameter to enable the sharing of reference clock refclk between all channels.
  • 0 : disable sharing
  • 1 : enable sharing
1
FIFO_OPTIONS Use this parameter to enable the FIFO in between user Avalon-ST and MAC interface.
  • 0: disable FIFO
  • 1: enable SC FIFO
  • 2: enable DC FIFO
  • 3: enable SC + DC FIFO
Note:

This parameter is available only for design example without IEEE 1588v2.

1
TSTAMP_FP_WIDTH Use this parameter to set the timestamp fingerprint width which follows the setting in 1G/10GbE MAC. You must regenerate the MAC IP if this parameter is changed. Enter the new width value in MAC IP regeneration page.
Note:

This parameter is available only for design example with IEEE 1588v2.

4