AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

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ID 683343
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY x
Features Requirements Design Example Walkthrough Components Parameters Design Example Testbench Clocking Scheme Reset Scheme Interface Signals Register Map Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Design Example Walkthrough x
Setting Up the Design Examples Changing Number of Channels Configuring PHY Speed IP Regeneration
Configuring PHY Speed x
Changing Speed between 10G and 1G in 1000BaseX mode Changing Speed between 1G, 100M, and 10M SGMII
Design Example Testbench x
Testbench Components Testbench Files Simulating Testbench Test Case
Simulating Testbench x
Using ModelSim Simulator Using VCS Simulator
Test Case x
Test Scenario for Design Example without IEEE 1588v2 Test Scenario for Design Example with IEEE 1588v2
Clocking Scheme x
Clocking Diagram Sync-E Support
Sync-E Support x
Enable Ref Clock Sharing Disable Ref Clock Sharing
Reset Scheme x
Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Design Example without IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Design Example with IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals MDIO Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals
Register Map x
Master TOD 1G TOD 10G TOD PHY 1G/10G MAC
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

Components

Figure 1. Block Diagram for Design Example without IEEE 1588v2


Figure 2.  Block Diagram for Design Example with IEEE 1588v2


Table 4.  Design Examples Components
Component Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Low latency Ethernet 10G MAC Ethernet MAC IP core
Intel® Arria® 10 1G/10G PHY Intel® FPGA 1G/10G and 10GBASE-KR PHY IP
MDIO Provides MDIO interface to connect Ethernet MAC to external PHY
Address decoder channel Address decoder module for each component within the channel, for example, MAC and PHY.
Address decoder multi-channel Address decoder module for all channels and components within multi-channel level, for example Master TOD.
Reset controller Reset modules which handle reset synchronisation for the components in the design example.
Master PLL Generates clocks for all the components in the design example.
Intel® Arria® 10 ATX PLL Generates a TX serial clock for Intel® Arria® 10 10G transceiver.
Intel® Arria® 10 fractional PLL Generates a TX serial clock for Intel® Arria® 10 1G transceiver.
Master Time-of-Day (TOD) — Provides a master TOD for all channels.
TOD Sync — Module to synch time of day from Master TOD to Local TOD for all channels.
Local TOD — TOD module in each channel.
Master Pulse Per Second module — Returns pulse per second (pps) to user for all channels.
1G/10G Pulse Per Second module — Returns pulse per second (pps) to user in each channel.
PTP packet classifier — Decodes the packet type of incoming PTP packets and returns the decoded information to the Ethernet MAC.
FIFO Avalon Streaming (Avalon-ST) single-clock or dual-clock FIFO that buffers the receive and transmit data between the MAC and client. —
Level Two Title