AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

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ID 683343
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY x
Features Requirements Design Example Walkthrough Components Parameters Design Example Testbench Clocking Scheme Reset Scheme Interface Signals Register Map Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Design Example Walkthrough x
Setting Up the Design Examples Changing Number of Channels Configuring PHY Speed IP Regeneration
Configuring PHY Speed x
Changing Speed between 10G and 1G in 1000BaseX mode Changing Speed between 1G, 100M, and 10M SGMII
Design Example Testbench x
Testbench Components Testbench Files Simulating Testbench Test Case
Simulating Testbench x
Using ModelSim Simulator Using VCS Simulator
Test Case x
Test Scenario for Design Example without IEEE 1588v2 Test Scenario for Design Example with IEEE 1588v2
Clocking Scheme x
Clocking Diagram Sync-E Support
Sync-E Support x
Enable Ref Clock Sharing Disable Ref Clock Sharing
Reset Scheme x
Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Design Example without IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Design Example with IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals MDIO Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals
Register Map x
Master TOD 1G TOD 10G TOD PHY 1G/10G MAC
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

Register Map

MSA0 is a 32-bit memory space address that provides access to all the client logic and scalable 1G/10G design example configuration registers. All registers in this space are 32-bit registers. Access smaller than 32 bits are not supported.

The following table shows the address offset for the design example and client logic at the design example level.

Table 14.  Design Example Block Register Map
Byte Offset Block
0x00_0000 - 0x00_EFFF Client Logic
0x00_F000 - 0x00_FFFF Intel® FPGA Logic
0x01_0000 Master TOD
0x02_0000 Port 0
0x03_0000 Port 1
0x04_0000 Port 2
0x05_0000 Port 3
0x06_0000 Port 4
0x07_0000 Port 5
0x08_0000 Port 6
0x09_0000 Port 7
0x0A_0000 Port 8
0x0B_0000 Port 9
0x0C_0000 Port 10
0x0D_0000 Port 11
0x0E_0000 onwards Client Logic

The following table shows the address offset for the design example and client logic for each port.

Table 15.   Port Sub-block Register Map
Byte Offset Sub-block
0x0000 - 0x3FFF Intel® FPGA Logic
0x4000 PHY
0x7800 10G TOD
0x7900 1G TOD
0x8000 1G/10G MAC
Level Two Title