AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
ID
683343
Date
11/06/2017
Public
MDIO Interface Signals
The following table lists the MDIO interface signals. These interface signals are applicable to both design examples.
Signal | Direction | Width | Description |
---|---|---|---|
mdio_mdc[] | output | [NUM_CHANNELS] | Management Data clock |
mdio_in[] | input | [NUM_CHANNELS] | Input to MDIO interface |
mdio_out[] | output | [NUM_CHANNELS] | Output from MDIO interface |
mdio_oen[] | output | [NUM_CHANNELS] | Output enable signal |