AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

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ID 683343
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY x
Features Requirements Design Example Walkthrough Components Parameters Design Example Testbench Clocking Scheme Reset Scheme Interface Signals Register Map Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Design Example Walkthrough x
Setting Up the Design Examples Changing Number of Channels Configuring PHY Speed IP Regeneration
Configuring PHY Speed x
Changing Speed between 10G and 1G in 1000BaseX mode Changing Speed between 1G, 100M, and 10M SGMII
Design Example Testbench x
Testbench Components Testbench Files Simulating Testbench Test Case
Simulating Testbench x
Using ModelSim Simulator Using VCS Simulator
Test Case x
Test Scenario for Design Example without IEEE 1588v2 Test Scenario for Design Example with IEEE 1588v2
Clocking Scheme x
Clocking Diagram Sync-E Support
Sync-E Support x
Enable Ref Clock Sharing Disable Ref Clock Sharing
Reset Scheme x
Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Design Example without IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Design Example with IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals MDIO Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals
Register Map x
Master TOD 1G TOD 10G TOD PHY 1G/10G MAC
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

PHY

PHY registers are applicable to both design examples.

The base address of the PHY registers are defined as follows:

Channel PHY Register Base Address
0 MSA0 + 0x02_4000
1 MSA0 + 0x03_4000
2 MSA0 + 0x04_4000
3 MSA0 + 0x05_4000
4 MSA0 + 0x06_4000
5 MSA0 + 0x07_4000
6 MSA0 + 0x08_4000
7 MSA0 + 0x09_4000
8 MSA0 + 0x0A_4000
9 MSA0 + 0x0B_4000
10 MSA0 + 0x0C_4000
11 MSA0 + 0x0D_4000
Note: For the description of each PHY register, refer to the Intel® Arria® 10 Transceiver PHY User Guide.
Note: The address offset in the following tables is in byte, while the register map table in the Intel® Arria® 10 Transceiver PHY User Guide is in word.
Table 19.  PMA Registers
Byte Offset Bit R/W Name
0x1110 1 RW reset_tx_digital
2 RW reset_rx_analog
3 RW reset_rx_digital
0x1184 RW phy_serial_loopback
0x1190 RW pma_rx_set_locktodata
0x1194 RW pma_rx_set_locktoref
0x1198 RO pma_rx_is_lockedtodata
0x119C RO pma_rx_is_lockedtoref
0x12A0 0 RW tx_invpolarity
1 RW rx_invpolarity
2 RW rx_bitreversal_enable
3 RW rx_bytereversal_enable
4 RW force_electrical_idle
0x12A4 0 R rx_syncstatus
1 R rx_patterndetect
2 R rx_rlv
3 R rx_rmfifodatainserted
4 R rx_rmfifodatadeleted
5 R rx_disperr
6 R rx_errdetect
Table 20.   PCS Registers
Byte Offset Bit R/W Name
0x1200 RW Indirect_addr
0x1204 2 RW RCLR_ERRBLK_CNT
3 RW RCLR_BER_COUNT
0x1208 1 RO HI_BER
2 RO BLOCK_LOCK
3 RO TX_FULL
4 RO RX_FULL
7 RO Rx_DATA_READY
Table 21.   Intel® Arria® 10 GMII PCS Registers
Byte Offset Bit R/W Name
0x1240 9 RW RESTART_AUTO_ NEGOTIATION
12 RW AUTO_NEGOTIATION_ ENABLE
15 RW Reset
0x1244 2 R LINK_STATUS
3 R AUTO_NEGOTIATION_ ABILITY
5 R AUTO_NEGOTIATION_ COMPLETE
0x1250 5 RW FD
6 RW HD
8:7 RW PS2,PS1
13:12 RW RF2,RF1
14 R0 ACK
15 RW NP
0x1254 5 R FD
6 R HD
8:7 R PS2,PS1
13:12 R RF2,RF1
14 R ACK
15 R NP
0x1258 0 R LINK_PARTNER_AUTO_NEGOTIATION_ABLE
1 R PAGE_RECEIVE
0x1288 15:0 RW AN link timer[15:0]
0x128C 4:0 RW AN link timer[4:0]
0x1290 0 RW SGMII_ENA
1 RW USE_SGMII_AN
3:2 RW SGMII_SPEED
Table 22.  10GBASE-KR Register Definitions
Byte Offset Bit R/W Name
0x12C0 0 RW Reset SEQ
1 RW Disable AN Timer
2 RW Disable LF Timer
6:4 RW SEQ Force Mode[2:0]
16 RW FEC ability
18 RW FEC request
0x12C4 0 R SEQ Link Ready
1 R SEQ AN timeout
2 R SEQ LT timeout
13:8 RW SEQ Reconfig Mode[5:0]
16 R KR FEC ability
17 R KR FEC err ind ability
Level Two Title