AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

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ID 683343
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY x
Features Requirements Design Example Walkthrough Components Parameters Design Example Testbench Clocking Scheme Reset Scheme Interface Signals Register Map Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Design Example Walkthrough x
Setting Up the Design Examples Changing Number of Channels Configuring PHY Speed IP Regeneration
Configuring PHY Speed x
Changing Speed between 10G and 1G in 1000BaseX mode Changing Speed between 1G, 100M, and 10M SGMII
Design Example Testbench x
Testbench Components Testbench Files Simulating Testbench Test Case
Simulating Testbench x
Using ModelSim Simulator Using VCS Simulator
Test Case x
Test Scenario for Design Example without IEEE 1588v2 Test Scenario for Design Example with IEEE 1588v2
Clocking Scheme x
Clocking Diagram Sync-E Support
Sync-E Support x
Enable Ref Clock Sharing Disable Ref Clock Sharing
Reset Scheme x
Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Design Example without IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Design Example with IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals MDIO Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals
Register Map x
Master TOD 1G TOD 10G TOD PHY 1G/10G MAC
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

10G TOD

10G TOD registers are only applicable to design examples with IEEE 1588v2.

The base address of the 10G TOD registers are defined as follows:

Channel 10G TOD Register Base Address
0 MSA0 + 0x02_7800
1 MSA0 + 0x03_7800
2 MSA0 + 0x04_7800
3 MSA0 + 0x05_7800
4 MSA0 + 0x06_7800
5 MSA0 + 0x07_7800
6 MSA0 + 0x08_7800
7 MSA0 + 0x09_7800
8 MSA0 + 0x0A_7800
9 MSA0 + 0x0B_7800
10 MSA0 + 0x0C_7800
11 MSA0 + 0x0D_7800
Table 18.   Register Description and Address Offset for 1588 TOD Clock
Byte Offset R/W Name Description HW Reset
0x0000 RW SecondsH
  • Bits 0 to 15: High-order 16-bit second field
  • Bits 16 to 31: Not used.
0x0
0x0004 RW SecondsL Bits 0 to 32: Low-order 32-bit second field. 0x0
0x0008 RW NanoSec Bits 0 to 32: 32-bit nanosecond field. 0x0
0x0010 RW Period
  • Bits 0 to 15: Period in fractional nanosecond
  • Bits 16 to 19: Period in nanosecond
  • Bits 20 to 31: Not used.
N
0x0014 RW AdjustPeriod The period for the offset adjustment.
  • Bits 0 to 15: Period in fractional nanosecond
  • Bits 16 to 19: Period in nanosecond
  • Bits 20 to 31: Not used.
0x0
0x0018 RW AdjustCount
  • Bits 0 to 19: The number of AdjustPeriod clock cycles used during offset adjustment
  • Bits 20 to 31: Not used.
0x0
0x001C RW DriftAdjust The drift of ToD adjusted periodically by adding a correction value as configured in this register space.
  • Bits 0 to 15: Adjustment value in fractional nanosecond (DRIFT_ADJUST_FNS). This value is added into the current ToD during the adjustment.
  • Bits 16 to 19: Adjustment value in nanosecond (DRIFT_ADJUST_NS). This value is added into the current ToD during the adjustment.
  • Bits 20 to 32: Not used.
 0x0
0x0020 RW DriftAdjustRate The count of clock cycles for each ToD’s drift adjustment to take effect.
  • Bits 0 to 15: The number of clock cycles (ADJUST_RATE). The ToD adjustment happens once after every period in number of clock cycles as indicated by this register space.
  • Bits 20 to 32: Not used.
 0x0
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