AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
ID
683343
Date
11/06/2017
Public
Multi Channel Level Reset Scheme
The following diagram shows the reset scheme at altera_eth_multi_channel_1588 level. master_reset_n is used to reset the whole design example, while channel_reset_n is used to reset the individual ethernet channel.
Reset Scheme at altera_eth_multi_channel_1588