AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Document Table of Contents

Reset Scheme

At the design example level, there are one master_reset_n and <N> channel_reset_n signals. All the signals are asynchronous and active-low signal. The signals are synced to different clock domain internally. When the master_reset_n is asserted, the signal will bring down all <N> Ethernet channels and all modules in the design example.

The channel_reset_n[0..N] only reset all the components in the individual channel.

Master reset is needed when the design example is powered up.