AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Document Table of Contents

Testbench Components

The testbench operates in loopback mode. The following figure shows the flow of the packets in the design examples.

Testbench Block Diagram for Design Examples

The following table lists the components in the testbench.

Testbench Components and Description
Component Description
Device under test (DUT) The design example.
Avalon driver Uses Avalon-ST master bus functional models (BFMs) to form transmit and receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-MM interfaces of the design example components.
Packet monitors Monitor transmit and receive datapaths, and display the frames in the simulator console.