AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Document Table of Contents

Test Scenario for Design Example without IEEE 1588v2

To perform test case, follow these steps:

  1. Set the start up with channel configured to 10G mode.
  2. Perform basic MAC configuration, PHY speed configuration and FIFO configuration for all 2 channels.
  3. Wait for the design example to assert the channel_ready signals for all 2 channels.
  4. Send the following packets:
    • Normal data frame, 64Bytes
    • SVLAN data frame, broadcast, 64Bytes
    • VLAN data frame, unicast, 500Bytes
  5. Repeat steps 2 to 4 for 1G, 100M and 10M speed mode.
  6. When the simulation ends, refer to the transcript window for channel 0 MAC TX and RX statistic counter results.
    Figure 3. Channel 0 MAC TX Statistic Counter
    Figure 4. Channel 0 MAC RX Statistic Counter

  7. If channel 0 Avalon_st RX interface successfully receives all 12 packets, the transcript displays PASSED.