Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. Adaptive Noise Reduction Intel® FPGA IP x
10.1. About the Adaptive Noise Reduction IP 10.2. Adaptive Noise Reduction IP Parameters 10.3. Adaptive Noise Reduction IP Functional Description 10.4. Adaptive Noise Reduction IP Registers 10.5. Adaptive Noise Reduction IP Software API
10.1. About the Adaptive Noise Reduction IP x
10.1.1. Adaptive Noise Reduction IP Performance and Resources
10.3. Adaptive Noise Reduction IP Functional Description x
10.3.1. Adaptive Noise Reduction IP Interfaces
11. Advanced Test Pattern Generator Intel® FPGA IP x
11.1. About the Advanced Test Pattern Generator IP 11.2. Advanced Test Pattern Generator IP Parameters 11.3. Advanced Test Pattern Generator IP Functional Description 11.4. Advanced Test Pattern Generator IP Registers 11.5. Advanced Test Pattern Generator IP Software API
11.1. About the Advanced Test Pattern Generator IP x
11.1.1. Advanced Test Pattern Generator IP Performance and Resources
11.3. Advanced Test Pattern Generator IP Functional Description x
11.3.1. Test Patterns 11.3.2. Dimensions, Offsets, and Alpha Settings 11.3.3. Run-time Settings 11.3.4. Advanced Test Pattern Generator IP Interfaces
12. AXI-Stream Broadcaster Intel® FPGA IP x
12.1. About the AXI-Stream Broadcaster IP 12.2. AXI-Stream Broadcaster IP Parameters 12.3. AXI-Stream Broadcaster IP Interfaces
12.1. About the AXI-Stream Broadcaster IP x
12.1.1. AXI-Stream Broadcaster IP Features 12.1.2. AXI-Stream Broadcaster IP Performance and Resources
13. Bits per Color Sample Adapter Intel FPGA IP x
13.1. About the Bits per Color Sample Adapter IP 13.2. Bits per Color Sample Adapter IP Parameters 13.3. Bits per Color Sample Adapter IP Interfaces 13.4. Bits per Color Sample Adapter IP Registers 13.5. Bits per Color Sample Adapter Software API
13.1. About the Bits per Color Sample Adapter IP x
13.1.1. Bits per Color Sample Adapter IP Performance and Resources
14. Black Level Correction Intel® FPGA IP x
14.1. About the Black Level Correction IP 14.2. Black Level Correction IP Parameters 14.3. Black Level Correction IP Functional Description 14.4. Black Level Correction IP Registers 14.5. Black Level Correction IP Software API
14.1. About the Black Level Correction IP x
14.1.1. Black Level Correction IP Performance and Resources
14.3. Black Level Correction IP Functional Description x
14.3.1. Black Level Correction IP Interfaces
15. Black Level Statistics Intel® FPGA IP x
15.1. About the Black Level Statistics IP 15.2. Black Level Statistics IP Parameters 15.3. Black Level Statistics IP Interfaces 15.4. Black Level Statistics IP Registers 15.5. Black Level Statistics IP Software API
15.1. About the Black Level Statistics IP x
15.1.1. Black Level Statistics IP Performance and Resources
16. Chroma Key Intel® FPGA IP x
16.1. About the Chroma Key IP 16.2. Chroma Key IP Parameters 16.3. Chroma Key IP Interfaces 16.4. Chroma Key Replacement 16.5. Chroma Key IP Registers 16.6. Chroma Key IP Software API
16.1. About the Chroma Key IP x
16.1.1. Chroma Key IP Performance and Resources
17. Chroma Resampler Intel® FPGA IP x
17.1. About the Chroma Resampler IP 17.2. Chroma Resampler IP Parameters 17.3. Chroma Resampler IP Functional Description 17.4. Chroma Resampler IP Registers 17.5. Chroma Resampler IP Software API
17.1. About the Chroma Resampler IP x
17.1.1. Chroma Resampler Performance and Resources
17.3. Chroma Resampler IP Functional Description x
17.3.1. Chroma Resampler IP Interfaces
18. Clipper Intel® FPGA IP x
18.1. About the Clipper IP 18.2. Clipper IP Parameters 18.3. Clipper IP Interfaces 18.4. Clipper IP Registers 18.5. Clipper IP Software API
18.1. About the Clipper IP x
18.1.1. Clipper IP Performance and Resources
19. Clocked Video Input Intel® FPGA IP x
19.1. About the Clocked Video Input IP 19.2. Initializing the Clocked Video Input IP 19.3. Clocked Video Input IP Parameters 19.4. Clocked Video Input IP Interfaces 19.5. Clocked Video Input IP Registers 19.6. Clocked Video Input IP Software API
19.1. About the Clocked Video Input IP x
19.1.1. Clocked Video Input IP Features 19.1.2. Clocked Video Input IP Performance and Resources
20. Clocked Video to Full-Raster Converter Intel® FPGA IP x
20.1. About the Clocked Video to Full-Raster Converter IP 20.2. Clocked Video to Full-Raster Converter Parameters 20.3. Clocked Video to Full-Raster Converter Block Description 20.4. Clocked Video Converter to Full-Raster IP Registers
20.1. About the Clocked Video to Full-Raster Converter IP x
20.1.1. Clocked Video to Full-Raster Converter Features 20.1.2. Clocked Video to Full-Raster Converter Performance and Resources
20.3. Clocked Video to Full-Raster Converter Block Description x
20.3.1. Clocked Video to Full-Raster Converter Interfaces
21. Clocked Video Output Intel® FPGA IP x
21.1. About the Clocked Video Output IP 21.2. Clocked Video Output IP Parameters 21.3. Clocked Video Output IP Functional Description 21.4. Clocked Video Output IP Interfaces 21.5. Clocked Video Output IP Registers 21.6. Clocked Video Output IP Software API
21.1. About the Clocked Video Output IP x
21.1.1. Clocked Video Output IP Performance and Resources 21.1.2. Clocked Video Output IP Features
22. Color Plane Manager Intel® FPGA IP x
22.1. About the Color Plane Manager IP 22.2. Color Plane Manager IP Parameters 22.3. Color Plane Manager IP Functional Description 22.4. Color Plane Manager IP Registers 22.5. Color Plane Manager Software API
22.1. About the Color Plane Manager IP x
22.1.1. Color Plane Manager IP Performance and Resources
22.3. Color Plane Manager IP Functional Description x
22.3.1. Color Plane Manager IP Interfaces
23. Color Space Converter Intel® FPGA IP x
23.1. About the Color Space Converter IP 23.2. Color Space Converter IP Parameters 23.3. Color Space Converter IP Functional Description 23.4. Color Space Converter IP Registers 23.5. Color Space Converter IP Software API
23.1. About the Color Space Converter IP x
23.1.1. Color Space Converter IP Features 23.1.2. Color Space Converter IP Performance and Resources
23.3. Color Space Converter IP Functional Description x
23.3.1. Color Space Converter IP Interfaces
24. Defective Pixel Correction Intel® FPGA IP x
24.1. About the Defective Pixel Correction IP 24.2. Defective Pixel Correction IP Parameters 24.3. Defective Pixel Correction IP Functional Description 24.4. Defective Pixel Correction IP Registers 24.5. Defective Pixel Correction IP Software API
24.1. About the Defective Pixel Correction IP x
24.1.1. Defective Pixel Correction IP Performance and Resources
24.3. Defective Pixel Correction IP Functional Description x
24.3.1. Defective Pixel Correction IP Interfaces
25. Deinterlacer Intel® FPGA IP x
25.1. About the Deinterlacer IP 25.2. Deinterlacer Parameters 25.3. Deinterlacer IP Functional Description 25.4. Deinterlacer IP Registers 25.5. Deinterlacer IP Software API
25.1. About the Deinterlacer IP x
25.1.1. Deinterlacer Performance and Resources
25.3. Deinterlacer IP Functional Description x
25.3.1. Deinterlacer Interfaces
26. Demosaic Intel® FPGA IP x
26.1. About the Demosaic IP 26.2. Demosaic IP Parameters 26.3. Demosaic IP Functional Description 26.4. Demosaic IP Registers 26.5. Demosaic IP Software API
26.1. About the Demosaic IP x
26.1.1. Demosaic IP Performance and Resources
26.3. Demosaic IP Functional Description x
26.3.1. Demosaic IP Interfaces
27. FIR Filter Intel® FPGA IP x
27.1. About the FIR Filter 27.2. FIR Filter Parameters 27.3. FIR Filter IP Operation 27.4. FIR Filter Interfaces 27.5. FIR Filter Registers 27.6. FIR Filter IP Software API
27.1. About the FIR Filter x
27.1.1. FIR Filter IP Performance and Resources
27.3. FIR Filter IP Operation x
27.3.1. FIR Filter Processing 27.3.2. FIR Filter Precision 27.3.3. FIR Coefficient Specification 27.3.4. FIR Filter Symmetry 27.3.5. Result to Output Data Type Conversion
27.3.4. FIR Filter Symmetry x
27.3.4.1. No Symmetry 27.3.4.2. Horizontal Symmetry 27.3.4.3. Vertical Symmetry 27.3.4.4. Horizontal and Vertical Symmetry 27.3.4.5. Diagonal Symmetry
28. Frame Cleaner Intel® FPGA IP x
28.1. About the Frame Cleaner IP 28.2. Frame Cleaner IP Parameters 28.3. Frame Cleaner IP Functional Description 28.4. Frame Cleaner IP Interfaces 28.5. Frame Cleaner IP Registers 28.6. Frame Cleaner IP Software API
28.1. About the Frame Cleaner IP x
28.1.1. Frame Cleaner IP Performance and Resources
29. Full-Raster to Clocked Video Converter Intel® FPGA IP x
29.1. About the Full-Raster to Clocked Video Converter 29.2. Full Raster to Clocked Video Converter Parameters 29.3. Full-Raster to Clocked Video Converter Block Description 29.4. Full-Raster to Clocked Video Converter Registers
29.1. About the Full-Raster to Clocked Video Converter x
29.1.1. Full-Raster to Clocked Video Converter Features 29.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
29.3. Full-Raster to Clocked Video Converter Block Description x
29.3.1. Full Raster to Clocked Video Converter Interfaces
30. Full-Raster to Streaming Converter Intel® FPGA IP x
30.1. About the Full-Raster to Streaming Converter IP 30.2. Full-Raster to Streaming Converter Parameters 30.3. Full-Raster to Streaming Converter Block Description
30.1. About the Full-Raster to Streaming Converter IP x
30.1.1. Full-Raster to Streaming Converter Features 30.1.2. Full-Raster to Streaming Converter Performance and Resources
30.3. Full-Raster to Streaming Converter Block Description x
30.3.1. Full-Raster to Streaming Converter Interfaces
31. Genlock Controller Intel® FPGA IP x
31.1. About the Genlock Controller IP 31.2. Genlock Controller IP Parameters 31.3. Genlock Controller IP Functional Description 31.4. Using Genlock Controller IP Software 31.5. Genlock Controller IP Registers 31.6. Genlock Controller IP Software API
31.1. About the Genlock Controller IP x
31.1.1. Genlock Controller IP Performance and Resources
31.3. Genlock Controller IP Functional Description x
31.3.1. Genlock Controller IP Interfaces
31.4. Using Genlock Controller IP Software x
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 31.4.3. Setting the VCXO hold over 31.4.4. Restarting the Genlock Controller IP 31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 31.4.7. Disturbing a Reference Clock (a cable pull)
32. Generic Crosspoint Intel® FPGA IP x
32.1. About the Generic Crosspoint IP 32.2. Generic Crosspoint IP Parameters 32.3. Generic Crosspoint IP Interfaces 32.4. Generic Crosspoint IP Registers 32.5. Generic Crosspoint IP Software API
32.1. About the Generic Crosspoint IP x
32.1.1. Generic Crosspoint IP Features 32.1.2. Generic Crosspoint Performance and Resources
33. Genlock Signal Router Intel® FPGA IP x
33.1. About the Genlock Signal Router IP 33.2. Genlock Signal Router IP Parameters 33.3. Genlock Signal Router IP Interfaces 33.4. Genlock Signal Router IP Registers 33.5. Genlock Signal Router IP Software API
33.1. About the Genlock Signal Router IP x
33.1.1. Genlock Signal Router IP Features 33.1.2. Genlock Signal Router IP Performance and Resources
34. Guard Bands Intel® FPGA IP x
34.1. About the Guard Bands IP 34.2. Guard Bands IP Parameters 34.3. Guard Bands IP Interfaces 34.4. Guard Bands IP Registers 34.5. Guard Bands IP Software API
34.1. About the Guard Bands IP x
34.1.1. Guard Bands IP Performance and Resources
35. Histogram Statistics Intel® FPGA IP x
35.1. About the Histogram Statistics IP 35.2. Histogram Statistics IP Parameters 35.3. Histogram Statistics IP Interfaces 35.4. Histogram Statistics IP Registers 35.5. Histogram Statistics IP Software API
35.1. About the Histogram Statistics IP x
35.1.1. Histogram Statistics IP Performance and Resources
36. Interlacer Intel® FPGA IP x
36.1. About the Interlacer IP 36.2. Interlacer IP Parameters 36.3. Interlacer IP Functional Description 36.4. Interlacer IP Registers 36.5. Interlacer IP Software API
36.1. About the Interlacer IP x
36.1.1. Interlacer IP Performance and Resources
36.3. Interlacer IP Functional Description x
36.3.1. Interlacer IP Interfaces
37. Mixer Intel® FPGA IP x
37.1. About the Mixer IP 37.2. Mixer IP Parameters 37.3. Mixer IP Functional Description 37.4. Mixer IP Registers 37.5. Mixer IP Software API
37.1. About the Mixer IP x
37.1.1. Mixer IP Performance and Resources
37.3. Mixer IP Functional Description x
37.3.1. Mixer IP Interfaces
38. Pixels in Parallel Converter Intel® FPGA IP x
38.1. About the Pixels in Parallel Converter IP 38.2. Pixels in Parallel Converter IP Parameters 38.3. Pixels in Parallel Converter Interfaces 38.4. Pixels in Parallel Converter Registers 38.5. Pixels in Parallel Converter IP Software API
38.1. About the Pixels in Parallel Converter IP x
38.1.1. Pixels in Parallel Converter IP Performance and Resources
39. Scaler Intel® FPGA IP x
39.1. About the Scaler 39.2. Scaler IP Parameters 39.3. Scaler IP Functional Description 39.4. Scaler IP Registers 39.5. Scaler IP Software API
39.1. About the Scaler x
39.1.1. Scaler IP Performance and Resources
39.2. Scaler IP Parameters x
39.2.1. Scaler Maximum Resolution
39.3. Scaler IP Functional Description x
39.3.1. Coefficient Selection 39.3.2. Coefficient Quantization 39.3.3. Filter Behavior at Edge Boundaries 39.3.4. Partial Frame Scaling 39.3.5. 422 and 420 Chroma Sampled Data Scaling 39.3.6. Scaler IP Interfaces
39.3.1. Coefficient Selection x
39.3.1.1. Updating Scaler IP Runtime Coefficients
40. Stream Cleaner Intel® FPGA IP x
40.1. About the Stream Cleaner IP 40.2. Stream Cleaner IP Parameters 40.3. Stream Cleaner IP Functional Description
40.1. About the Stream Cleaner IP x
40.1.1. Stream Cleaner IP Performance and Resources
40.3. Stream Cleaner IP Functional Description x
40.3.1. Stream Cleaner IP Interfaces
41. Switch Intel® FPGA IP x
41.1. About the Switch IP 41.2. Switch IP Parameters 41.3. Switch IP Functional Description 41.4. Switch IP Registers 41.5. Switch IP Software API
41.1. About the Switch IP x
41.1.1. Switch IP Performance and Resources
41.3. Switch IP Functional Description x
41.3.1. Switch IP Latency 41.3.2. Switch IP Interfaces
42. Tone Mapping Operator Intel® FPGA IP x
42.1. About the Tone Mapping Operator IP 42.2. TMO IP Parameters 42.3. TMO IP Block Description 42.4. TMO IP Registers 42.5. TMO IP Software API
42.1. About the Tone Mapping Operator IP x
42.1.1. TMO IP Features 42.1.2. TMO IP Performance and Resource Utilization
42.3. TMO IP Block Description x
42.3.1. TMO IP Interfaces 42.3.2. TMO IP Latency
43. Test Pattern Generator Intel® FPGA IP x
43.1. About the Test Pattern Generator IP 43.2. Test Pattern Generator IP Parameters 43.3. Test Pattern Generator IP Functional Description 43.4. Test Pattern Generator IP Registers 43.5. Test Pattern Generator IP Software API
43.1. About the Test Pattern Generator IP x
43.1.1. Test Pattern Generator IP Performance and Resources
43.3. Test Pattern Generator IP Functional Description x
43.3.1. Test Patterns 43.3.2. Output Subsampling and Color Space 43.3.3. Run-time Settings 43.3.4. Test Pattern Generator IP Interfaces
44. Unsharp Mask Intel® FPGA IP x
44.1. About the Unsharp Mask IP 44.2. Unsharp Mask IP Parameters 44.3. Unsharp Mask IP Functional Description 44.4. Unsharp Mask IP Registers 44.5. Unsharp Mask IP Software API
44.1. About the Unsharp Mask IP x
44.1.1. Unsharp Mask IP Performance and Resources
44.3. Unsharp Mask IP Functional Description x
44.3.1. Unsharp Mask IP Interfaces
45. Video and Vision Monitor Intel FPGA IP x
45.1. About the Video and Vision Monitor IP 45.2. Video and Vision Monitor IP Parameters 45.3. Video and Vision Monitor IP Functional Description 45.4. Video and Vision Monitor IP Registers 45.5. Video and Vision Monitor Software API
45.1. About the Video and Vision Monitor IP x
45.1.1. Video and Vision Monitor IP Performance and Resources
45.3. Video and Vision Monitor IP Functional Description x
45.3.1. Video and Vision Monitor IP Interfaces
46. Video Frame Buffer Intel® FPGA IP x
46.1. About the Video Frame Buffer IP 46.2. Video Frame Buffer IP Parameters 46.3. Video Frame Buffer IP Functional Description 46.4. Video Frame Buffer IP Registers 46.5. Video Frame Buffer IP Software API
46.1. About the Video Frame Buffer IP x
46.1.1. Video Frame Buffer Performance and Resources
46.3. Video Frame Buffer IP Functional Description x
46.3.1. Video Frame Buffer IP Interfaces
47. Video Frame Reader Intel FPGA IP x
47.1. About the Video Frame Reader IP 47.2. Video Frame Reader IP Parameters 47.3. Video Frame Reader IP Functional Description 47.4. Video Frame Reader IP Registers 47.5. Video Frame Reader IP Software API
47.1. About the Video Frame Reader IP x
47.1.1. Video Frame Reader IP Performance and Resources
47.3. Video Frame Reader IP Functional Description x
47.3.1. Video Frame Reader IP Interfaces
48. Video Frame Writer Intel FPGA IP x
48.1. About the Video Buffer Writer IP 48.2. Video Frame Writer IP Parameters 48.3. Video Frame Writer IP Functional Description 48.4. Video Frame Writer IP Registers 48.5. Video Frame Writer IP Software API
48.1. About the Video Buffer Writer IP x
48.1.1. Video Frame Writer IP Performance and Resources
48.3. Video Frame Writer IP Functional Description x
48.3.1. Video Frame Writer IP Interfaces
49. Video Streaming FIFO Intel® FPGA IP x
49.1. About the Video Streaming FIFO IP 49.2. Video Streaming FIFO IP Parameters 49.3. Video Streaming FIFO IP Interfaces
49.1. About the Video Streaming FIFO IP x
49.1.1. Video Streaming FIFO IP Performance and Resources
50. Video Timing Generator Intel® FPGA IP x
50.1. About the Video Timing Generator IP 50.2. Video Timing Generator IP Parameters 50.3. Video Timing Generator IP Functional Description 50.4. Video Timing Generator IP Interfaces 50.5. Video Timing Generator IP Registers 50.6. Video Timing Generator IP Software API
50.1. About the Video Timing Generator IP x
50.1.1. Video Timing Generator IP Features 50.1.2. Video Timing Generator IP Performance and Resources
51. Vignette Correction Intel® FPGA IP x
51.1. About the Vignette Correction IP 51.2. Vignette Correction IP Parameters 51.3. Vignette Correction IP Interfaces 51.4. Vignette Correction IP Registers 51.5. Vignette Correction IP Software API
51.1. About the Vignette Correction IP x
51.1.1. Vignette Correction IP Performance and Resources
52. Warp Intel® FPGA IP x
52.1. About the Warp IP 52.2. Warp IP Parameters 52.3. Warp IP Block Description 52.4. Warp IP Registers 52.5. Warp IP Software API
52.1. About the Warp IP x
52.1.1. Warp IP Features 52.1.2. Warp IP Performance and Resource Utilization
52.3. Warp IP Block Description x
Coefficient Tables Warp Mesh Interpolation Output Pixel Interpolation and Filtering Blank Skip Regions Easy Warp Single Memory Bounce Single Memory Bounce Cache Example Transform Compression Limits and Mipmaps 52.3.1. Block Cache Tool 52.3.2. Warp IP Interfaces 52.3.3. Warp IP Latency 52.3.4. External Memory for Warp IP
52.5. Warp IP Software API x
52.5.1. Using Warp IP Software 52.5.2. Warp IP Software Code Examples
53. White Balance Correction Intel® FPGA IP x
53.1. About the White Balance Correction IP 53.2. White Balance Correction IP Parameters 53.3. White Balance Correction IP Functional Description 53.4. White Balance Correction IP Registers 53.5. White Balance Correction IP Software API
53.1. About the White Balance Correction IP x
53.1.1. White Balance Correction IP Performance and Resources
53.3. White Balance Correction IP Functional Description x
53.3.1. White Balance Correction IP Interfaces
54. White Balance Statistics Intel® FPGA IP x
54.1. About the White Balance Statistics IP 54.2. White Balance Statistics IP Parameters 54.3. White Balance Statistics IP Interfaces 54.4. White Balance Statistics IP Registers 54.5. White Balance Statistics IP Software API
54.1. About the White Balance Statistics IP x
54.1.1. White Balance Statistics IP Performance and Resources
55. Design Security x
55.1. Memory Subsystems 55.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Tone Mapping Operator Intel® FPGA IP
43. Test Pattern Generator Intel® FPGA IP
44. Unsharp Mask Intel® FPGA IP
45. Video and Vision Monitor Intel FPGA IP
46. Video Frame Buffer Intel® FPGA IP
47. Video Frame Reader Intel FPGA IP
48. Video Frame Writer Intel FPGA IP
49. Video Streaming FIFO Intel® FPGA IP
50. Video Timing Generator Intel® FPGA IP
51. Vignette Correction Intel® FPGA IP
52. Warp Intel® FPGA IP
53. White Balance Correction Intel® FPGA IP
54. White Balance Statistics Intel® FPGA IP
55. Design Security
56. Document Revision History for Video and Vision Processing Suite User Guide

52.3. Warp IP Block Description

The Warp IP accepts RGB or YUV format video input from its Intel FPGA streaming video interface and directly stores the video data in external memory. The video input process has a pool of four frame buffers that it uses to store the incoming video data. The IP accesses the buffers in a cyclic order.

The video output process generates RGB or YUV format Intel FPGA streaming video using the warped image data.

The IP generates arbitrary warps based on a transform mesh. If you turn on Use easy warp, it offers a fixed set of transforms (rotations and mirroring) without needing a transform mesh. If you turn off Use easy warp, the IP processes the buffered input video by the configured number of warp engines to apply the required warp. Three coefficient tables control the warp engines to define the warp that the IP applies. External memory stores the three coefficient tables that are generated using the Warp IP software API.

The IP defines the required warp with a backward mapping from the output to the input pixel positions. It represents the warp as a subsampled mesh that defines the mapping in 8x8 or 16x16 regions. For output pixel mappings within the 8x8 or 16x16 positions, the warp engine applies bilinear interpolation. For any input image dimensions (height or width) that are greater than 3840, use a 16x16 mesh.

If you turn off Use single memory bounce, the IP operates with two bounces through external memory. The IP buffers the input video and it writes back the resultant warped image to external memory into one of two output video buffers. The IP writes to these dual output buffers alternately. The IP reads the warped image in the output video buffers and passes out of the IP.

If you turn on Use single memory bounce, the IP operates with just a single bounce through external memory—the buffering of the input video. The IP transfers the resultant warped image directly to the video output process without passing through external memory.

Figure 134. Warp IP block diagram (Double Memory Bounce)

The figure shows a high-level block diagram for the Warp IP with its connection to external memory when Use single memory bounce is off. In this configuration, the engines read and write video data through the external memory.

Figure 135. Warp IP block diagram (Single Memory Bounce)The figure shows a high-level block diagram for the Warp IP with its connection to external memory when Use single memory bounce is on. In this configuration, the engines only read video data from the external memory. The engines transmit their video data directly to the output process without the data passing through external memory.
Figure 136. Warp image transform examplesFrom left: arbitrary warp with a 5x5 array of control points, four corner warp with some radial distortion.

Coefficient Tables

Each engine within the Warp IP has read access to its own set of three coefficient tables that define and control the image transform that the IP applies. The three different tables are:

  • Mesh coefficients that define the output to input pixel transform
  • Fetch coefficients that control the loading of the input image into the cache memory within the engine(s).
  • Filter coefficients that control the mapping from the cache memory as the IP generates the interpolated or filtered output pixels.

The format of the mesh coefficients is different to the mesh data that you provide to the software API. The Software API uses 32-bit signed integers for the mesh values; the Warp IP uses a 16-bit offset binary format.

The IP needs just the mesh data to define the warp. The software API uses this mesh data to generate the required coefficient tables.

Warp Mesh Interpolation

The IP defines the warp transform using either an 8x8 or 16x16 subsampled mesh. This mesh defines the mapping from the output pixel positions to the corresponding input pixel positions. Thesubsampled mesh requires that only the mappings for the following output pixel positions are defined:

8x8 mesh

(0,0), (8,0), (16,0) … (W, 0)
(0,8), (8,8), (16,8) … (W, 8)
.
(0,H), (8, H), (16, H) … (W, H)

where W=8*ceil(image width/8) and H=8*ceil(image height/8)

16x16 mesh 
(0,0), (16,0), (32,0) … (W, 0)
(0,16), (16,16), (32,16) … (W, 16)
 . 
(0,H), (16, H), (32, H) … (W, H)

where W=16*ceil(image width/16) and H=16*ceil(image height/16)

Using either the 8x8 or 16x16 mesh is based on the input image size. If either the input image width or height is greater than 3840, you must use a 16x16 mesh. If both the input image width and height are equal to or less than 3840, you must use an 8x8 mesh.

To generate the output pixel positions that lie in between these 8x8 or 16x16 positions, the Warp IP uses bilinear interpolation.

Output Pixel Interpolation and Filtering

The IP generates output pixels with the pixel data from the associated input pixel positions as defined by the warp that the IP applies. The IP generates output pixel values with a bicubic interpolation calculation using a 4x4 kernel of the associated input pixel values.

The weightings for the interpolation over the 4x4 kernel are a combination of a bicubic function and a variable low pass filtering function. The software API automatically applies low pass filtering, which it bases on the amount of downscaling that results for that region of the warp.

When Use mipmaps is on, the Warp IP software automatically identifies regions of the output image that require the downscaled, mipmap images and the interpolation and filtering settings are chosen accordingly.

Blank Skip Regions

When you configure the Warp IP to substantially downscale regions of an image, large areas of the output image can map to points outside the input image. These unmapped regions result in the IP producing black.

Because these regions in the output image do not require any processing of the input image by the Warp IP, for efficiency the IP skips the processing associated with these regions. This skipping process is setup automatically by the software API which determines, from the desired warp mapping, which regions the IP skips. You see this behavior only when Use single memory bounce is off.

Easy Warp

When you turn on Use easy warp:

  • The IP supports rotations of 0°, 90°, 180° and 270° and you can apply a horizontal mirror operation before the selected rotation.
  • The IP does not configure any engines.
  • The IP applies the required rotational or mirrored transform by the video output block as it reads data from external memory.
  • The IP does not require any processing engines, giving resource savings and memory bandwidth savings.

When Use easy warp is on, ensure that both Use mipmaps and Use single memory bounce are off.

For easy warp rotations of 0 or 180°, the maximum input width dimension must not exceed the maximum output width. You set the maximum width with the Maximum output video width parameter. For easy warp rotations of 90° or 270°, the transposing of vertical and horizontal dimensions places restrictions on the input resolution.

Table 1064.  Input Resolution Restrictions for 90° or 270°
Maximum Output Video Width Input Height Restriction
2048 1088
3840 2176
Figure 137. Warp IP block diagram (Easy Warp)

The figure shows a high-level block diagram for the Warp IP with Use Easy warp with its connection to external memory.

Figure 138. Easy Warp image transform examplesFrom top left clockwise: original image, mirrored, 90° rotate and 180° rotate.

Single Memory Bounce

Generally, turning on Use single memory bounce gives reduced memory bandwidth compared to when it is off. However, single memory bounce may require larger internal RAM. The RAM usage depends on the specific warp transform. For some transforms the IP requires larger amounts of cache. Any increased cache requirement requires increased internal block RAM usage.

With Use single memory bounce on, three cache size options are available: 256, 512 and 1024 cache blocks per engine. With Use single memory bounce off, the IP has a fixed cache size of 256 cache blocks per engine.

Whether you turn on Use single memory bounce depends on the actual transform the IP performs. Intel provides a software tool that determines how much cache the IP needs to process the desired transform. You provide the tool with information such as the input and output resolutions, the transform required, and the number of engines to use. The tool then provides guidance on how much cache to use to process the transform.

For information on the Warp block cache tool, refer to Block Cache Tool. For information on the memory bandwidth implications of running with a single memory bounce, refer to External Memory for Warp IP.

Single Memory Bounce Cache Example

An example of cache usage is given based on a 45 degree rotation with UHD input and output resolutions at 60 fps on an Intel Arria 10 device. This throughput requires that the IP uses two engines.

With Use single memory bounce off, the block RAM usage by the IP is 365 M20Ks.

With Use single memory bounce on, the IP requires 512 cache blocks per engine because of the constraints of the 45 degree rotation. This cache block requirement translates to a block RAM usage of 407 M20Ks.

Table 1065.  Block RAM Usage – UHD 45 Degree Rotate
Use single memory bounce Cache blocks per engine Total block RAM usage
On 512 407
Off 256 (fixed) 365

Transform Compression Limits and Mipmaps

There is a fundamental compression limit of 2:1 in the way the Warp IP applies the required transform in generating the output image. This limit comes from the low-pass filtering performed during the interpolation calculation and from the structure of the cache blocks used in the pixel processing. The limit may be overcome by using downscaled versions of the input image as the source data in the interpolation and filtering stage.

The figures show how you may use un this way the downscaled versions of the input image, available as a pyramid of the various downscale factorsy.

Figure 139. Transform Compression Limit with Use mipmaps offUsing only the original image in the application of the transform gives a final compression limit of 2:1.
Figure 140. Transform Compression Limit with Use mipmaps onUsing the original image and a pyramid of downscaled images in the application of the transform gives a final compression limit of 256:1.

When Use mipmaps is on, the Warp IP automatically generates and uses this pyramid of downscaled input images as required by the transform it performs.


Section Content
Block Cache Tool
Warp IP Interfaces
Warp IP Latency
External Memory for Warp IP

Related Information
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