Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

14.4. Black Level Correction IP Registers

Each register is either read-only (RO) or read-write (RW).

Table 147.  Black Level Correction RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_BLC as appropriate and with an optional REG suffix
Address Register Access Description
Lite 34 Full
Parameterization registers
0x0000 VID_PID RO N/A

Read this register to retrieve the ID of the IP.

This register always returns 0x6FA7_0177.

0x0004 VERSION RO N/A Read this register to retrieve the version information for the IP.
0x0008 LITE_MODE RO N/A

Read this register to determine if Lite mode is on.

This register always returns 1.

0x000C DEBUG_ENABLED RO N/A

Read this register to determine if Debug features are on.

This register returns 0 for off and 1 for on.

0x0010 BPS_IN RO N/A Read this register to determine the Input bits per color symbol.
0x0014 BPS_OUT RO N/A

Read this register to determine the Output bits per color symbol.

0x0018 NUM_COLOR_IN RO N/A

Read this register to determine the Number of color planes at the input.

This register always returns 1.

0x001C NUM_COLOR_OUT RO N/A

Read this register to determine the Number of color planes at the output.

This register always returns 1.

0x0020 PIP RO N/A Read this register to determine the Number of pixels in parallel.
0x0024 MAX_WIDTH RO N/A Read this register to determine the Maximum field width.
0x0028 MAX_HEIGHT RO N/A Read this register to determine the Maximum field height.
0x002C REFLECT_AROUND_ZERO RO N/A Read this register to determine Reflect around zero.
0x0030 to 0x011F - - - Reserved
Control, debugging, and statistics registers
0x0120 IMG_INFO_WIDTH RW N/A The expected width of the incoming video fields.
0x0124 IMG_INFO_HEIGHT RW N/A The expected height of the incoming video fields.
0x0028 to 0x013F - - - Reserved
0x0140 STATUS RO N/A

Read this register for information about the IP status.

0x0144 FRAME_STATS RO N/A

Read this register for some frame statistics.

0x0148

COMMIT RW N/A Write any value to this register to submit changes to the control, black pedestal, and color scaler registers.
0x014C CONTROL RW N/A

Control bits and fields of the IP

0x0150 CFA_00_BLACK_PEDESTAL RW N/A Black Pedestal value for color channel 0.
0x0154 CFA_00_COLOR_SCALER RW N/A Color scaler value for color channel 0.
0x0158 CFA_01_BLACK_PEDESTAL RW N/A Black Pedestal value for color channel 1.
0x015C CFA_01_COLOR_SCALER RW N/A Color scaler value for color channel 1.
0x0160 CFA_10_BLACK_PEDESTAL RW N/A Black Pedestal value for color channel 2.
0x0164 CFA_10_COLOR_SCALER RW N/A Color scaler value for color channel 2.
0x0168 CFA_11_BLACK_PEDESTAL RW N/A Black Pedestal value for color channel 3.
0x016C CFA_11_COLOR_SCALER RW N/A Color scaler value for color channel 3.
0x0170 to 0x01FF - - - Reserved

Register Bit Descriptions

Table 148.   STATUS
Name Bits Description
Reserved 31:2 Reserved.
Commit 1 Pending commit
Running 0 When 1, the IP is processing data.
Table 149.   FRAME_STATS
Name Bits Description
Reserved 31:8 Reserved.
Checksum 7:0 A simple checksum of the frame
Table 150.   CONTROL
Name Bits Description
Reserved 31:4 Reserved. Write 0.
Clip Zero En 3 You may set this bit to override reflection if Reflect around zero is on. The IP clips values below black level to 0 instead of reflecting them around 0.
Color filter array phase 2:1 Specifies 2x2 color filter order starting from the top left corner of the image.
 00  01   10  11
C0C1 C1C0 C2C3 C3C2
C2C3 C3C2 C0C1 C1C0
Bypass 0 Set to bypass Black Level Correction IP. When set the IP passes the input image unmodified.
Table 151.   CFA_00_BLACK_PEDESTAL
Name Bits Description
Reserved 31:Input bits per color sample Reserved. Write 0.
Black pedestal Input bits per color sample - 1:0

Black pedestal value for color channel 0 (C0).

Table 152.   CFA_00_COLOR_SCALER
Name Bits Description
Reserved 31:18 Reserved. Write 0.
Color scaler 17:0

Unsigned 0.18 fixed-point color scaler for color channel 0 (C0). MSBs to LSBs correspond to the binary digits 2-1 to 2-18.

Table 153.   CFA_01_BLACK_PEDESTAL
Name Bits Description
Reserved 31:Input bits per color sample Reserved. Write 0.
Black pedestal Input bits per color sample - 1:0

Black pedestal value for color channel 1 (C1).

Table 154.   CFA_01_COLOR_SCALER
Name Bits Description
Reserved 31:18 Reserved. Write 0.
Color scaler 17:0

Unsigned 0.18 fixed-point color scaler for color channel 1 (C1). MSBs to LSBs correspond to the binary digits 2-1 to 2-18.

Table 155.   CFA_10_BLACK_PEDESTAL
Name Bits Description
Reserved 31:Input bits per color sample Reserved. Write 0.
Black pedestal Input bits per color sample - 1:0

Black pedestal value for color channel 2 (C2).

Table 156.   CFA_10_COLOR_SCALER
Name Bits Description
Reserved 31:18 Reserved. Write 0.
Color scaler 17:0

Unsigned 0.18 fixed-point color scaler for color channel 2 (C2). MSBs to LSBs correspond to the binary digits 2-1 to 2-18.

Table 157.   CFA_11_BLACK_PEDESTAL
Name Bits Description
Reserved 31:Input bits per color sample Reserved. Write 0.
Black pedestal Input bits per color sample - 1:0

Black pedestal value for color channel 3 (C3).

Table 158.   CFA_11_COLOR_SCALER
Name Bits Description
Reserved 31:18 Reserved. Write 0.
Color scaler 17:0

Unsigned 0.18 fixed-point color scaler for color channel 3 (C3). MSBs to LSBs correspond to the binary digits 2-1 to 2-18.

34 Registers are RW only if you also turn on Debug features, otherwise they are WO.