Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

7.5. Protocol Converter IP Registers

Read and write access to the register map is via the Avalon memory-mapped compliant av_mm_control_agent interface. Turn on Memory-mapped control interface, for access to this interface and access to the register map.
Table 11.  Protocol Converter IP Parameterization RegistersIn the software API these register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_PROTOCOL_CONV as appropriate and with an optional REG suffix
Address Register Access Description
0x0000 VID_PID RO

Read this register to retrieve the protocol converter vendor ID and product ID.

This register always returns 6AF7_023D.

0x0004 VERSION RO

Read this register for the IP version information.

0x0008 CONVERSION_MODE RO

A read to this register returns a value that specifies the input and output protocols for this instance of the Protocol Converter IP.

0 = Avalon streaming video to Intel FPGA streaming video Lite

1 = Intel FPGA streaming video Lite to Avalon streaming video

2 = Avalon streaming video to Intel FPGA streaming video Full

3 = Intel FPGA streaming video Full to Avalon streaming video

4 Intel FPGA streaming video Lite to Intel FPGA streaming video Full

5 = Intel FPGA streaming video Full to Intel FPGA streaming video Lite

0x000C DEBUG_ENABLED RO A read to this register returns the value you select for the Enable debug parameter in this instance of the Protocol converter. The host software can read this value to determine which registers you can read
0x0010 to 0x011F - - Unused.
Table 12.  Protocol Converter IP Control and Debug RegistersIn the software API these register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_PROTOCOL_CONV as appropriate and with an optional REG suffix For more information, refer to Control Packets.
Address Register Access 5 Description
Not Full Full
0x0120 IMG_INFO_WIDTH RW RO

When the input protocol is Intel FPGA streaming video lite, use this register to set the expected width of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the width that the protocol converter derives from information in the image information packet. This register is unused if the input protocol is Avalon streaming video.

0x0124 IMG_INFO_HEIGHT RW RO

When the input protocol is Intel FPGA streaming video lite, use this register to set the expected height of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the height that the protocol converter derives from information in the image information packet. This register is unused if the input protocol is Avalon streaming video.

0x0128 IMG_INFO_INTERLACE RW RO

When the input protocol is Intel FPGA streaming video lite, use this register to set the expected interlacing of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the interlace code that the protocol converter derives from information in the image information packet. This register is unused if the input protocol is Avalon streaming video.

0x012C Reserved - - Reserved.
0x0130 IMG_INFO_COLORSPACE RW RO

When the input protocol is Intel FPGA streaming video lite or Avalon streaming video, use this register to set the expected color space of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the color space that the protocol converter derives from information in the image information packet.

0x0134 IMG_INFO_SUBSAMPLING RW RO

When the input protocol is Intel FPGA streaming video lite or Avalon streaming video, use this register to set the expected chroma sampling of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the chroma sampling that the protocol converter derives from information in the image information packet.

0x0138 IMG_INFO_COSITING RW RO

When the input protocol is Intel FPGA streaming video lite or Avalon streaming video, use this register to set the expected co-siting of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the cositing that the protocol converter derives from information in the image information packet.

0x013C IMG_INFO_FIELD_COUNT - RO When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the field count that the protocol converter derives from information in the image information packet. Unused if the input protocol is Avalon streaming video or Intel FPGA streaming video lite.
0x0140 STATUS RO The value you read from this register indicates the processing status of the IP.
0x0144 FIELD_COUNT RO Only used if the output protocol is Intel FPGA streaming video full. A read to this register returns the value of the internal field count, which increments after each output field. The IP uses it to populate the field count values in the output image info and end of frame packets.
0x0148 VIP_WIDTH RO If you select Avalon Streaming Video, for Input protocol variant, a read to this register returns the frame width in the most recently received control packet. The width that the IP reports is a literal decode of the information in the control packet. If the data the IP processes is 4:2:0 chroma sampled, the width that the IP reports is half the actual frame or frame width.
0x014C VIP_HEIGHT RO If you select Avalon Streaming Video for Input protocol variant, a read to this register returns the frame height specified in the most recently received control packet.
0x0150 VIP_INTERLACE RO If you select Avalon Streaming Video for Input protocol variant, a read to this register returns the interlace nibble specified in the most recently received control packet.
0x0154 CTRL RW Writes to this register instruct the IP to start processing video frames, or to stop processing at the next frame boundary. Write a 1 to bit[0] of this register to start the IP. Write a 0 to bit[0] to stop at the next frame boundary. If the IP is already at a frame boundary or is between frames when the write to stop occurs, it stops immediately and does not begin the next frame. The value of this register resets to 0, so if the av_mm_control_agent interface is turned on, the IP resets into the stopped state and you must write a 1 to bit[0] to begin processing.
0x0158 FIELD_COUNT_RESET RW Any write to this register resets the value of the internal field count to zero. The value you write is unimportant. Only if the output protocol is Intel FPGA streaming video full.
0x015C Reserved - Reserved.

Register Bit Descriptions

Table 13.  VID_PID
Name Bits Description
Protocol converter vendor and product ID 31:0 This register always returns 6AF7_023D.
  • 15:0 is the product ID and always returns 6AF7_023D
  • 31:16 is the vendor ID and is always going to be 0x6AF7
Table 14.  VERSION
Name Bits Description
Register map version 7:0 Register map version.
IP patch revision 15:8 -
IP update revision 23:16 Updated when the IP version changes.
IP major revision 31:24 Updated when the IP version changes.
Table 15.  CONVERSION_MODE
Name Bits Description
Conversion mode 31:0

Returns the protocol conversion mode.

0 = Avalon streaming video to Intel FPGA streaming video lite

1 = Intel FPGA streaming video lite to Avalon streaming video

2 = Avalon streaming video to Intel FPGA streaming video full

3 = Intel FPGA streaming video full to Avalon streaming video

4 = Intel FPGA streaming video lite to Intel FPGA streaming video full

5 = Intel FPGA streaming video full to Intel FPGA streaming video lite

Table 16.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 31:0 Returns 1 if you turn on Debug features and 0 otherwise.
Table 17.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

For parameterizations with Intel FPGA streaming video lite input, write to this register to set the expected width of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 18.   IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

For parameterizations with Intel FPGA streaming video lite input, write to this register to set the expected height of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register reads the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 19.   IMG_INFO_INTERLACE
Name Bits Description
IntlaceNibble bits 3:0

For parameterizations with Intel FPGA streaming video lite input, write to this register to set the expected interlacing of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features enabled, this register returns the intlaceNibble field from the most recently received image information packet .

unused 31:4 Unused.
Table 20.  IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0

For parameterizations with Intel FPGA streaming video lite or Avalon streaming video input, write to this register to set the expected color space of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the 7 bit CSP field from the most recently received image information packet .

unused 31:7  
Table 21.  IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0

For parameterizations with Intel FPGA streaming video lite or Avalon streaming video input, write to this register to set the expected subsampling of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 22.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

For parameterizations with Intel FPGA streaming video lite or Avalon streaming video input, write to this register to set the expected co-siting of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the COSITE field from the most recently received image information packet.

unused 31:2 Unused.
Table 23.   IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0 For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.
unused 31:7 Unused.
Table 24.  STATUS
Name Bits Description
Status bit 0

This bit indicates the IP is currently processing a frame. A value of 1 indicates that the IP is busy processing, a value of 0 indicates that it is idle.

When the input uses the Intel FPGA streaming video lite protocol, the interpretation of bit 0 depends on if you turn on Enable low latency mode. If you turn on Enable low latency mode, the IP sets bit 0 to 1 when it receives the first pixel of the frame and sets it to 0 when it receives the number of lines specified in register map (address 0x124). The IP holds bit 0 at 0 while it flushes any additional lines. If you do not turn on Enable low latency mode, the IP sets bit 0 to 1 at the start of the first frame received and it remains high until you reset the IP.

When the input uses the Intel FPGA streaming video full protocol or Avalon streaming video, the end of a frame sequence is clearly marked by the protocol and bit 0 of the status can be deasserted between frames

Frame processed bit 1 This bit indicates if the IP has fully processed at least one frame since the last reset. A 1 indicates that the IP has processed at least one, a 0 indicates that the IP has processed no frames.
unused 2 This bit indicates if the last frame the IP receives has the expected number of pixels. A 0 indicates that the frame matched the expected width and height. A 1 indicates that the frame had too many or too few pixels according to these settings.
Table 25.  FIELD_COUNT
Name Bits Description
Field count 31:0 Current value of the internal field counter.
Table 26.  VIP_WIDTH
Name Bits Description
VIP width 15:0 Field width specified in the last Avalon streaming video control packet received at the input.
unused 31:16 Unused.
Table 27.  VIP_HEIGHT
Name Bits Description
VIP height 15:0 Field height specified in the last Avalon streaming video control packet received at the input.
unused 31:16 Unused.
Table 28.  VIP_INTERLACE
Name Bits Description
VIP interlace 3:0 Interlace nibble specified in the last Avalon streaming video control packet received at the input.
unused 31:4 Unused.
Table 29.  CTRL
Name Bits Description
Start / stop bit 0 Write 1 to this bit to start the IP, write 0 to stop the IP.
unused 31:1 Unused.
Table 30.  FIELD_COUNT_RESET
Name Bits Description
unused 31:0 Unused.
5

The function of each of these registers and the access permission, varies depending on which protocol you select for the input interface. The registers are read only (RO) if the input interface is Intel FPGA streaming video full, and RW if the input interface is either Intel FPGA streaming video lite or Avalon streaming video. If the registers are RW, they are only readable if you turn on Debug features parameter.