Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

38.4. Pixels in Parallel Converter Registers

Each register is either read-only (RO) or read-write (RW). Writes to RO registers complete but the IP ignores them. A read to any RW register also completes, but returns undefined data by default. These registers are RW to save FPGA resources. To read back the values you write to these registers, you must turn on Debug features when you configure the IP.
Table 670.  Pixels in Parallel IP RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_CLIPPER as appropriate and with an optional REG suffix
Address Register Access Description
Parameterization registers
0x0000 VID_PID RO

Read this register to retrieve the pixels in parallel converter product ID.

This register always returns 0x6AF7_0239.

0x0004 VERSION RO

Read this register for the IP version information.

0x0008 LITE_MODE RO

Read this register to determine if Lite mode is on.

This register always returns 1 as the Avalon memory-mapped control interface is only available when you turn on Lite mode.

0x000C DEBUG_ENABLED RO

Read this register to determine if Debug features is on.

This register returns 1 if reads to other registers designated as RW return the last value the IP writes to the register, or an undefined value.

0x0010 to 0x011F - - Unused
Control and debug registers

For more information, refer to Control Packets

0x0120 IMG_INFO_WIDTH RW Set the expected width of incoming video fields.
0x0124 to 0x0130 - - Unused.
0x0134 IMG_INFO_SUBSAMPLING RW The expected chroma subsampling of the incoming video fields.
0x0138 to 0x013C - - Unused.
0x0140 STATUS RO

Bit 0: Status bit.

1 means the pixels in parallel converter is processing a video field, 0 otherwise.

Register Bit Descriptions

Table 671.  VID_PID
Name Bits Description
Pixels in parallel converter version ID and product ID 31:0 This register always returns 0x6AF7_0239.
  • 15:0 is the product ID and always returns 0x0239
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 672.  VERSION
Name Bits Description
Register map version 7:0 Register map version.
IP patch revision 15:8 -
IP update revision 23:16 Updated when the IP version changes.
IP major revision 31:24 Updated when the IP version changes.
Table 673.   LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on Lite mode.
Unused 31:1 Unused.
Table 674.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 675.  IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0 Write to this register to set the expected width of the incoming video fields.
unused 31:16 Unused.
Table 676.  IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0 Write to this register to set the expected chroma sub-sampling of the incoming video fields.
unused 31:2 Unused.
Table 677.  STATUS
Name Bits Description
Status bit 0 1 means the pixels in parallel converter is processing a video field, 0 otherwise.
unused 31:1 Unused.