Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

11.3.3. Run-time Settings

If the Advanced Test Pattern Generator IP Memory-mapped control interface is on, you can adjust at run time the resolution, interlace settings, pattern configuration and mixer configuration via the register map. Changing the settings at runtime differs depending on whether the IP is parameterized to output the full or lite variant of the Intel FPGA streaming video protocol.

If off, the IP only uses parameters prefixed with Fixed to configure resolution, interlace, mixer and pattern configuration.

For resolution, interlace and pattern dimensions, offsets, alpha settings, write to the COMMIT register (address 0x14C) to apply the settings at the next frame boundary. If the settings you provide cause a pattern to clip partially or wholly off-screen, the IP does not show it.

For pattern configuration settings, write to PATTERN_X_SELECT (0x1E8) the pattern number you want to apply the settings to at the next frame boundary. Only the pattern configuration relevant to the pattern selected has an effect. You may write to PATTERN_X_SELECT multiple times a frame, to apply different settings to each of the patterns enabled.

Unlike other video and vision IP registers, you do not need to write to the COMMIT register after writing to any of the pattern registers.

The full sequence to update the registers for resolution, interlace, and pattern dimensions, offsets, alpha settings is:

  1. Make required edits to anywhere within the subset of the resolution, interlace and mixer registers (addresses 0x150 to 0x1E4).
  2. Write any value to the COMMIT register (0x14C) to commit the changes as a coherent set.
  3. Do not make any further edits to the settings until the IP deasserts the pending bit of the STATUS register (0x140); this occurs at the next field boundary after the write to the COMMIT register at which points the IP applies the settings.
  4. When the IP deasserts bit 1 of the STATUS register, you can make further edits..

The full sequence to update the register for pattern configuration is:

  1. Make all edits to the subset of pattern configuration registers (0x1E8 onwards). You must write to all registers related to the type of pattern you wish to configure, otherwise there may be data left from a previous write.
  2. Write a number X to PATTERN_X_SELECT to apply the changes to Pattern X.
    1. Ensure that the changes you make apply for the type of Pattern X. This can be checked by reading PATTERN_X_TYPE (0x24 to 0x40).
    2. Writing to PATTERN_X_SELECT automatically commit the registers such that all changes apply to the next field. You do not need to write to the COMMIT register afterwards for these specific registers.
  3. Repeat steps 1-2 for every pattern you want to change.