Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

51.4. Vignette Correction IP Registers

Each register is either read-only (RO) or read-write (RW). Tables are write-only (WO).
Table 1026.  Vignette Correction IP RegistersIn the software API, the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_VC as appropriate and with an optional REG suffix
Address Register Access Description
Lite 165 Full
Parameterization registers
0x00000 VID_PID RO N/A

Read this register to retrieve the ID of the IP.

This register always returns 0x6FA7_0178.

0x00004 VERSION RO N/A Read this register to retrieve the version information for the IP.
0x00008 LITE_MODE RO N/A

Read this register to determine if lite mode is on.

This register always returns 1.

0x0000c DEBUG_ENABLED RO N/A

Read this register to determine if Debug features are on.

This register returns 0 for off and 1 for on.

0x00010 BPS_IN RO N/A Read this register to determine the bits per symbol for the input data.
0x00014 BPS_OUT RO N/A Read this register to determine the bits per symbol for the output data.
0x00018 NUM_COLOR_IN RO N/A

Read this register to determine the number of color planes for the input data.

0x0001c NUM_COLOR_OUT RO N/A

Read this register to determine the number of color planes for the output data.

0x00020 PIP RO N/A Read this register to determine the number of pixels in parallel.
0x00024 MAX_WIDTH RO N/A Read this register to determine the maximum supported input field width.
0x00028 MAX_HEIGHT RO N/A Read this register to determine the maximum supported input field height.
0x0002c CFA_ENABLE RO N/A Read this register to determine if Color filter array is on. When on, the IP operates with a 2x2 color filter array with 4 color channels. When off, the IP operates with 1 color plane and multiple color panes per pixel.
0x00030 MAX_GAIN_MESH_POINTS RO N/A Read this register to determine the maximum number of mesh points.
0x00034 PER_COLOR_GAIN_ENABLE RO N/A Read this register to determine the per color or shared coefficient tables.
0x00038 to 0x0011F - - - Reserved
Control, debug, and statistics registers
0x00120 IMG_INFO_WIDTH RW N/A The expected width of the incoming video fields.
0x00124 IMG_INFO_HEIGHT RW N/A The expected height of the incoming video fields.
0x00128 to 0x0013F - - - Reserved
0x00140 STATUS RO N/A

Read this register for information about the IP status.

0x00144 FRAME_STATS RO N/A

Read this register for some frame statistics.

0x00148 COMMIT RW N/A

Write to this register to submit changes to the control and setup registers.

0x0014C CONTROL RW N/A

Control bits and fields of the IP

0x00150 BLOCK_PIX_COUNT RW N/A

Number of pixel columns in a base zone

0x00154 BLOCK_LINE_COUNT RW N/A Number of pixel lines in a base zone
0x00158 H_NUM_BLOCKS RW N/A Number of horizontal zones
0x0015C V_NUM_BLOCKS RW N/A Number of vertical zones
0x00160 H_RAMP_FRAC_BITS RW N/A Fractional part of the horizontal ramp increments for a base zone size
0x00164 H_RAMP_P1_FRAC_BITS RW N/A Fractional part of the horizontal ramp increments for an extended zone size
0x00168 H_RAMP_M1_FRAC_BITS RW N/A Fractional part of the horizontal ramp increments for the last column of zones
0x0016C V_RAMP_FRAC_BITS RW N/A Fractional part of the vertical ramp increments for a base zone size
0x00170 V_RAMP_P1_FRAC_BITS RW N/A Fractional part of the vertical ramp increments for an extended zone size
0x00174 V_RAMP_M1_FRAC_BITS RW N/A Fractional part of the vertical ramp increments for the last line of zones

0x00178 to

0x001FF

- - - Reserved

0x00200 to

0x00200+M-1

166
CP0_MESH_GAIN_TABLE WO N/A

The IP uses this table for all color channels if Independent color plane correction mesh gain coefficients parameter is off.

0x00200+M to 0x041ff

166
- - - Reserved

0x04200 to

0x04200+M-1

166
CP1_MESH_GAIN_TABLE WO N/A

The IP uses this table only if Independent color plane correction mesh gain coefficients is on and color channel 1 exists. Otherwise, all registers in this table are reserved.

0x04200+M to

0x081ff

166
- - - Reserved

0x08200 to

0x08200+M-1

166
CP2_MESH_GAIN_TABLE WO N/A

The IP uses this table only if Independent color plane correction mesh gain coefficients is on and color channel 2 exists. Otherwise, all registers in this table are reserved.

0x08200+M to

0x0C1ff

166
- - - Reserved

0x0C200

to 0x0C200+M-1

166
CP3_MESH_GAIN_TABLE WO N/A

The IP uses this table only if Independent color plane correction mesh gain coefficients is on and color channel 3 exists. Otherwise, all registers in this table are reserved.

0x0C200+M to

0x101ff

166
- - - Reserved
0x10200

to

0x10200+M-1 166
STEP_LUT_TABLE WO N/A

This is a complementary table shared across all color channels, enabling the IP to achieve fine grained precision at the corners and edges of the mesh boundaries.

The IP expects V x H mesh entries to be stored in raster order, left to right and top to bottom. The number of entries V x H must remain less than or equal to the Maximum number of correction mesh points parameter.

The top left mesh point of any given mesh box is the reference table entry point for the V and H step functions.

0x10200+M to

0x201FF

166
- - - Reserved

Register Bit Descriptions

Table 1027.   STATUS
Name Bits Description
Reserved 31:2 Reserved
Commit 1 Commit is pending
Running 0 When 1, the IP is processing data..
Table 1028.   FRAME_STATS
Name Bits Description
Reserved 31:8 Reserved
Checksum 7:0 A simple checksum of the frame.
Table 1029.   CONTROL
Name Bits Description
Reserved 31:3 Reserved. Write 0.
Color filter Array Phase. 2:1 Specifies 2x2 color filter order starting from the top left corner of the image.
 00  01   10  11
C0C1 C1C0 C2C3 C3C2
C2C3 C3C2 C0C1 C1C0
Bypass 0 Set to bypass the IP. When set the IP passes the input image unmodified.
Table 1030.   BLOCK_PIX_COUNT
Name Bits Description
Reserved 31:16 Reserved.
Value 15:0

The mesh box boundary in pixels. The IP determines when to load the next mesh gain coefficient while moving in the horizontal direction by reading this register. The value of this register must be:

floor((Frame Width / H_NUM_BLOCKS) / PIP).

You can use the H Step LUT to make up the remainders.

Table 1031.   BLOCK_LINE_COUNT
Name Bits Description
Reserved 31:16 Reserved.
Value 15:0

The mesh box boundary in lines. The IP determines when to load the next mesh gain coefficient while moving in the vertical direction by reading this register. The value of this register must be:

floor(Frame Height / V_NUM_BLOCKS)

You can use the V Step LUT to make up the remainders for a given mesh box.

Table 1032.   H_NUM_BLOCKS
Name Bits Description
Reserved 31:16 Reserved.
Value 15:0

The number of mesh boxes in the horizontal direction, which is the number of horizontal mesh points minus 1. The IP supports arbitrary V x H rectangular mesh blocks, where valid values of H range from 8 to 512 in 1 step increments. The value of V x H must remain less than or equal to the Maximum number of correction mesh points parameter.

Table 1033.   V_NUM_BLOCKS
Name Bits Description
Reserved 31:16 Reserved.
Value 15:0

The number of mesh boxes in the vertical direction, which is the number of vertical mesh points minus 1. The IP supports arbitrary V x H rectangular mesh blocks, where valid values of V range from 8 to 512 in 1 step increments. The value of V x H must remain less than or equal to the Maximum number of correction mesh points parameter.

Table 1034.   H_RAMP_FRAC_BITS
Name Bits Description
Reserved 31:22 Reserved.
Value 21:0

The horizontal ramp fractional bits. This is the fraction of corrective gain for each horizontal pixel step within a mesh box. The value of this register must be:

1 / BLOCK_PIX_COUNT

Table 1035.   H_RAMP_P1_FRAC_BITS
Name Bits Description
Reserved 31:22 Reserved.
Value 21:0

An alternative horizontal ramp fractional bits register for removing reminders. The IP uses this register when the H Step LUT indicates a +1 version for a given mesh box. The value of this register must be:

1 / (BLOCK_PIX_COUNT+1)

Table 1036.   H_RAMP_M1_FRAC_BITS
Name Bits Description
Reserved 31:22 Reserved.
Value 21:0

A third alternative horizontal ramp fractional bits register, for when the IP is processing the final mesh column. It allows fine alignment to the top right mesh gain value. The value of this register must be:

(((1 / (BLOCK_PIX_COUNT – 1)) – H_RAMP_FRAC_BITS) / PIP) + H_RAMP_FRAC_BITS – k

The k is 1 for PIP>1, otherwise 0.

Table 1037.   V_RAMP_FRAC_BITS
Name Bits Description
Reserved 31:22 Reserved.
Value 21:0

The vertical ramp fractional bits. It is the fraction of corrective gain for each vertical pixel step within a mesh box. The value of this register must be:

1 / BLOCK_LINE_COUNT

Table 1038.   V_RAMP_P1_FRAC_BITS
Name Bits Description
Reserved 31:22 Reserved.
Value 21:0

An alternative vertical ramp fractional bits register for removing reminders. The IP uses this register when the V Step LUT indicates a +1 version for a given mesh box. The value of this register must be:

1 / (BLOCK_LINE_COUNT+1)

Table 1039.   V_RAMP_M1_FRAC_BITS
Name Bits Description
Reserved 31:22 Reserved.
Value 21:0

A third alternative vertical ramp fractional bits register, for when the IP is processing the final mesh line. It allows fine alignment to the bottom mesh gain values.

The value of this register must be:

1 / (BLOCK_LINE_COUNT -1)

Table 1040.   CP0_MESH_GAIN_TABLE
Name Bits Description
Reserved 31:19 Reserved.
Coefficient 18:0

Unsigned 8.11 fixed point mesh coefficient table for color channel 0. The IP expects V x H mesh entries to be stored in raster order, left to right and top to bottom. The number of entries V x H must remain less than or equal to the Maximum number of correction mesh points parameter.

Table 1041.   CP1_MESH_GAIN_TABLE
Name Bits Description
Reserved 31:19 Reserved.
Coefficient 18:0

Unsigned 8.11 fixed point mesh coefficient table for color channel 1. The IP expects V x H mesh entries to be stored in raster order, left to right and top to bottom. The number of entries V x H must remain less than or equal to the Maximum number of correction mesh points parameter.

Table 1042.   CP2_MESH_GAIN_TABLE
Name Bits Description
Reserved 31:19 Reserved.
Coefficient 18:0

Unsigned 8.11 fixed point mesh coefficient table for color channel 2. The IP expects V x H mesh entries to be stored in raster order, left to right and top to bottom. The number of entries V x H must remain less than or equal to the Maximum number of correction mesh points parameter.

Table 1043.   CP3_MESH_GAIN_TABLE
Name Bits Description
Reserved 31:19 Reserved.
Coefficient 18:0

Unsigned 8.11 fixed point mesh coefficient table for color channel 3. The IP expects V x H mesh entries to be stored in raster order, left to right and top to bottom. The number of entries V x H must remain less than or equal to the Maximum number of correction mesh points parameter.

Table 1044.   STEP_LUT_TABLE
Name Bits Description
Reserved 31:17 Reserved.
H comp enable for the PIP instance 8. 16

Reserved if PIP<8.

167
H step enable for the PIP instance 8. 15

Reserved if PIP<8.

168
H comp enable for the PIP instance 7. 14

Reserved if PIP<8.

167
H step enable for the PIP instance 7 13

Reserved if PIP<8.

168
H comp enable for the PIP instance 6 12

Reserved if PIP<8.

167
H step enable for the PIP instance 6 11

Reserved if PIP<8.

168
H comp enable for the PIP instance 5 10

Reserved if PIP<8.

167
H step enable for the PIP instance 5 9

Reserved if PIP<8.

168
H comp enable for the PIP instance 4. 8

Reserved if PIP<4.

167
H step enable for the PIP instance 4 7

Reserved if PIP<4.

168
H comp enable for the PIP instance 3 6

Reserved if PIP<4.

167
H step enable for the PIP instance 3 5

Reserved if PIP<4.

168
H comp enable for the PIP instance 2 4

Reserved if PIP<2.

167
H step enable for the PIP instance 2. 3

Reserved if PIP<2.

168
H comp enable 2

Compensates for the fractional pixel distances from the last mesh point for PIP instance 1.

167
H step enable. 1

For this mesh point, adds 1 to the pixel count for PIP instance 1, effectively stretching the mesh box by PIP pixels. You must set all entries across a mesh column to the same value for consistency.

168
V step enable 0 For this mesh point, adds 1 to the line count, stretching the mesh box by 1 pixel line. You must set all entries across a mesh line to the same value for consistency.
165

In lite mode, registers are RW only if you also turn on Debug features, otherwise they are WO.

166

M = 4 × Maximum number of correction mesh points

167 The IP uses H comp enable to compensate for fractional precision when the width of the frame is not an integer multiple of (H_NUM_BLOCKS x PIP). You must set H comp enable to 0 by default. If a final remainder that is not divisible by PIP exists, in the final mesh box column you must set H comp enable to 1 for all PIP instances.
168 The IP uses H step enable to remove remainders.When the remainder is greater than or equal to PIP, you must set H step enable for a mesh box column of choice for all PIP instances. However, Intel recommends distributing those mesh box columns across the width of the frame uniformly. Continue until the remainder is less than PIP, where you must set H step enable only for the remaining pixels in the final mesh box column.