Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

52.2. Warp IP Parameters

The IP offers various compile-time parameters.
Table 1062.  Warp IP Parameters
Parameter Values Description
Video data format
Lite mode On The IP only operates in Lite mode, with no support for control packets.
Number of pixels in parallel 1, 2, 4, or 8 Number of pixels processed in parallel. When Use easy warp is on, the IP supports only 1 or 2 pixels in parallel.
Number of color planes 3 Number of color planes per pixel.
Bits per color sample 10 Number of bits per color sample
Maximum input video width 2048, 3840, 4096, or 7680. Maximum number of pixels per input line. Configures the depth of line buffers in the video input block.

The IP can process image widths of up to 7680. When Use easy warp is on, the maximum video width is limited to 2048 or 3840.

Maximum output video width 2048, 3840, 4096, or 7680. Maximum number of pixels per output line. Configures the depth of line buffers in the video output block. When Use easy warp is on, the maximum video width is limited to 2048 or 3840.
Configuration Settings
Use easy warp On or off

Turn on for a limited set of warp operations. Turn off for arbitrary warps.

The IP can only process image heights and widths that are a multiple of two when you select 2 pixels in parallel and turn on Use easy warp.

Memory frame buffer size SD, HD, UHD, or 8K

The amount of memory space the IP allocates to each frame buffer.

Each pixel is 4 bytes in size.

  • SD is 1024x1024 pixels
  • HD is 2048x2048 pixels
  • UHD is 4096x4096 pixels
  • 8K is 8192x8192 pixels
Enable Debug Registers On or off Turn on to read back various registers containing debugging information.

Engine Configuration Settings

(These parameters are only available when Use easy warp is off)

Number of engines 1, 2 or, 4 Number of processing engines to use. Each engine processes one pixel per clock cycle.
Use mipmaps On or off When you turn on Use mipmaps, the IP uses a pyramid of automatically downscaled mipmap images to support arbitrary warps with downscaled regions up to 256:1. When you turn off Use mipmaps, arbitrary warps are limited to downscaled regions up to 2:1.

When Number of pixels in parallel is 1 or 2, the IP does not support turning on Use mipmaps with a Memory frame buffer size of 8K

Use single memory bounce On or off

Defines how the engines are connected to and use the external memory. When you turn off Use single memory bounce the engines both read and write their video data through the memory (double memory bounce). When you turn on Use single memory bounce the engines only read video data from memory and their output data passes directly to the video output process of the warp IP.

The IP can only generate image heights that are a multiple of 8 lines when you turn on Use single memory bounce.

Cache blocks per engine 256, 512 or 1024 Only available when Use single memory bounce is on. Defines the amount of cache memory that is available to each engine. The amount of cache memory required is a function of the input resolution the IP processes, the required warp and the number of engines you select.
Figure 133. Warp IP GUIWhen Use easy warp is on, ensure that both Use mipmaps and Use single memory bounce are off.
Table 1063.  Warp IP throughput for different parameters
Number of pixels in parallel The number of processing engines to use fMAX (MHz) Performance
1 1 150 Image resolutions of up to 1920x1080 at 60 fps.
1 1 300 Image resolutions of up to 3840x2160 at 30 fps.
2 2 300 Image resolutions of up to 3840x2160 at 60 fps.
1 1 600
4 4 600 Image resolutions of up to 3840x2160 at 120 fps or 7680x4320 at 30 fps.