Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

13.4. Bits per Color Sample Adapter IP Registers

Each register is either read-only (RO) or read-write (RW).

In the software API the register names appear with a prefix of INTEL_VVP,INTEL_VVP_CORE or INTEL_VVP_PIXEL_ADAPTER as appropriate and with an optional REGsuffix.

Table 123.  Parameterization Registers
Address Register Access Description
0x0000 VID_PID RO Read this register for the Bits per Color Sample Adapter product ID. This register always returns 6AF7_024C
0x0004 VERSION RO Read this register for the IP version information.
0x0008 LITE_MODE RO Read this register to determine if lite mode is on. This register returns 0 when you turn off lite mode and 1 when you turn on lite mode.
0x000C DEBUG_ENABLED RO Read this register to determine if Debug features is on. This register returns 1 if reads to other registers designated as RW return the last value the IP writes to the register, or an undefined value.
0x0010 BPS_IN RO Read this register to determine the number of bits that represent each color plane on the input tdata bus
0x0014 BPS_OUT RO Read this register to determine the number of bits that represent each color plane on the output tdata bus
0x0018 to 0x011F - - Unused.
Table 124.  Control and Debug RegistersFor more information, refer to Control Packets. You must turn on debug features to read the values stored in these registers. If you turn off debug features, reads to these registers return undefined data. The only exception is the STATUS register, the value of which you can always read
Address Register

Access

Description
0x0120 IMG_INFO_WIDTH RO When you turn on Debug features, this register returns the width that the Bits per Color Sample Adapter derives from information in the image information packet.
0x0124 IMG_INFO_HEIGHT RO When you turn on Debug features, this register returns the height that the Bits per Color Sample Adapter derives from information in the image information packet.
0x0128 IMG_INFO_INTERLACE RO When you turn on Debug features, this register returns the interlace nibble that the Bits per Color Sample Adapter derives from information in the image information packet.
0x012C Reserved - Reserved.
0x0130 IMG_INFO_COLORSPACE RO When you turn on Debug features, this register returns the color space that the Bits per Color Sample Adapter derives from information in the image information packet.
0x0134 IMG_INFO_SUBSAMPLING RO When you turn on Debug features, this register returns the subsampling that the Bits per Color Sample Adapter derives from information in the image information packet.
0x0138 IMG_INFO_COSITING RO When you turn on Debug features, this register returns the cositing that the Bits per Color Sample Adapter derives from information in the image information packet.
0x013C IMG_INFO_FIELD_COUNT RO When you turn on Debug features, this register returns the field count that the Bits per Color Sample Adapter derives from information in the image information packet.
0x0140 STATUS RO

Bit0: Status bit.

1 means Bits per Color Sample Adapter is processing a video field, 0 otherwise.

Bit1: Pendingregister updates bit.

Any writes to the output sampling register (0x0148) cause the IP to raise the pending register updates bit, to indicate outstanding changes to the resampling settings.

The IP lowers this bit at the next field boundary after a write to the COMMIT register.

0x0144 COMMIT RW The IP holds any changes to output bits per color value via the register map until you send a write to this register. The value you write is unimportant.
0x0148 IMG_INFO_BPS_OUT RW Write the value for the bits per color field for outgoing image information packets to this register. You write the actual bits per color value. The value for the image information packet is bits per color minus one, but the IP performs the subtraction.

Register Bit Descriptions

Table 125.  VID_PID
Name Bits Description
Bits per Color Sample Adapter vendor ID and product ID 31:0

This register always returns 0x6AF7_024C.

  • 15:0 is the product ID and always returns 0x024C
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 126.  VERSION
Name Bits Description
Register map version 7:0 Register map version.
IP patch revision 15:8 -
IP update revision 23:16 Updated when the IP version changes.
IP major revision 31:24 Updated when the IP version changes.
Table 127.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 31:0 The IP only uses this register when Lite mode is off. Reads to this register always return 0
Table 128.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 31:0 Returns 1 if you turn on Debug features and 0 otherwise.
Table 129.  BPS_IN
Name Bits Description
Bits per color in 31:0 Returns the number of bits that represent each color plane on the input tdata bus
Table 130.  BPS_OUT
Name Bits Description
Bits per color out 31:0 Returns the number of bits that represent each color plane on the output tdata bus
Table 131.  IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0 When you turn on Debug features, this register reads the width-1 field from the most recently received image information packet and adds 1 to return a value for width.
unused 31:16 Unused.
Table 132.  IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0 When you turn on Debug features, this register reads the height-1 field from the most recently received image information packet and adds 1 to return a value for height.
unused 31:16 Unused.
Table 133.  IMG_INFO_INTERLACE
Name Bits Description
IntlaceNibble bits 3:0

When you turn on Debug features, this register returns the intlaceNibble field from the most recently received image information packet.

Unused 31:4 Unused.
Table 134.  IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0 When you turn on Debug features, this register returns the 7 bit CSP field from the most recently received image information packet.
unused 31:7 Unused.
Table 135.  IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0 When you turn on Debug features, this register returns the SUBSA field from the most recently received image information packet.
Unused 31:2 Unused.
Table 136.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0 When you turn on Debug features, this register returns the COSITE field from the most recently received image information packet.
unused 31:2 Unused.
Table 137.  IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0 When you turn on Debug features, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.
unused 31:7 Unused.
Table 138.  STATUS
Name Bits Description
Status bit 0 1 means Bits per Color Sample Adapter is processing a video field, 0 otherwise.
Pending register updates bit 1 1 means Bits per Color Sample Adapter has pending updates, 0 otherwise
Unused 31:2 Unused.
Table 139.  COMMIT
Name Bits Description
Unused 31:0 Unused.
Table 140.  IMG_INFO_BPS_OUT
Name Bits Description
Image info bps out 4:0 Value the IP uses for the bits per color sample field in outgoing image information packers. You should write the true value for the number of bits per color and the IP subtracts 1 from this value to create the correct value for output.
Unused 31:5 Unused.