Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. Adaptive Noise Reduction Intel® FPGA IP x
10.1. About the Adaptive Noise Reduction IP 10.2. Adaptive Noise Reduction IP Parameters 10.3. Adaptive Noise Reduction IP Functional Description 10.4. Adaptive Noise Reduction IP Registers 10.5. Adaptive Noise Reduction IP Software API
10.1. About the Adaptive Noise Reduction IP x
10.1.1. Adaptive Noise Reduction IP Performance and Resources
10.3. Adaptive Noise Reduction IP Functional Description x
10.3.1. Adaptive Noise Reduction IP Interfaces
11. Advanced Test Pattern Generator Intel® FPGA IP x
11.1. About the Advanced Test Pattern Generator IP 11.2. Advanced Test Pattern Generator IP Parameters 11.3. Advanced Test Pattern Generator IP Functional Description 11.4. Advanced Test Pattern Generator IP Registers 11.5. Advanced Test Pattern Generator IP Software API
11.1. About the Advanced Test Pattern Generator IP x
11.1.1. Advanced Test Pattern Generator IP Performance and Resources
11.3. Advanced Test Pattern Generator IP Functional Description x
11.3.1. Test Patterns 11.3.2. Dimensions, Offsets, and Alpha Settings 11.3.3. Run-time Settings 11.3.4. Advanced Test Pattern Generator IP Interfaces
12. AXI-Stream Broadcaster Intel® FPGA IP x
12.1. About the AXI-Stream Broadcaster IP 12.2. AXI-Stream Broadcaster IP Parameters 12.3. AXI-Stream Broadcaster IP Interfaces
12.1. About the AXI-Stream Broadcaster IP x
12.1.1. AXI-Stream Broadcaster IP Features 12.1.2. AXI-Stream Broadcaster IP Performance and Resources
13. Bits per Color Sample Adapter Intel FPGA IP x
13.1. About the Bits per Color Sample Adapter IP 13.2. Bits per Color Sample Adapter IP Parameters 13.3. Bits per Color Sample Adapter IP Interfaces 13.4. Bits per Color Sample Adapter IP Registers 13.5. Bits per Color Sample Adapter Software API
13.1. About the Bits per Color Sample Adapter IP x
13.1.1. Bits per Color Sample Adapter IP Performance and Resources
14. Black Level Correction Intel® FPGA IP x
14.1. About the Black Level Correction IP 14.2. Black Level Correction IP Parameters 14.3. Black Level Correction IP Functional Description 14.4. Black Level Correction IP Registers 14.5. Black Level Correction IP Software API
14.1. About the Black Level Correction IP x
14.1.1. Black Level Correction IP Performance and Resources
14.3. Black Level Correction IP Functional Description x
14.3.1. Black Level Correction IP Interfaces
15. Black Level Statistics Intel® FPGA IP x
15.1. About the Black Level Statistics IP 15.2. Black Level Statistics IP Parameters 15.3. Black Level Statistics IP Interfaces 15.4. Black Level Statistics IP Registers 15.5. Black Level Statistics IP Software API
15.1. About the Black Level Statistics IP x
15.1.1. Black Level Statistics IP Performance and Resources
16. Chroma Key Intel® FPGA IP x
16.1. About the Chroma Key IP 16.2. Chroma Key IP Parameters 16.3. Chroma Key IP Interfaces 16.4. Chroma Key Replacement 16.5. Chroma Key IP Registers 16.6. Chroma Key IP Software API
16.1. About the Chroma Key IP x
16.1.1. Chroma Key IP Performance and Resources
17. Chroma Resampler Intel® FPGA IP x
17.1. About the Chroma Resampler IP 17.2. Chroma Resampler IP Parameters 17.3. Chroma Resampler IP Functional Description 17.4. Chroma Resampler IP Registers 17.5. Chroma Resampler IP Software API
17.1. About the Chroma Resampler IP x
17.1.1. Chroma Resampler Performance and Resources
17.3. Chroma Resampler IP Functional Description x
17.3.1. Chroma Resampler IP Interfaces
18. Clipper Intel® FPGA IP x
18.1. About the Clipper IP 18.2. Clipper IP Parameters 18.3. Clipper IP Interfaces 18.4. Clipper IP Registers 18.5. Clipper IP Software API
18.1. About the Clipper IP x
18.1.1. Clipper IP Performance and Resources
19. Clocked Video Input Intel® FPGA IP x
19.1. About the Clocked Video Input IP 19.2. Initializing the Clocked Video Input IP 19.3. Clocked Video Input IP Parameters 19.4. Clocked Video Input IP Interfaces 19.5. Clocked Video Input IP Registers 19.6. Clocked Video Input IP Software API
19.1. About the Clocked Video Input IP x
19.1.1. Clocked Video Input IP Features 19.1.2. Clocked Video Input IP Performance and Resources
20. Clocked Video to Full-Raster Converter Intel® FPGA IP x
20.1. About the Clocked Video to Full-Raster Converter IP 20.2. Clocked Video to Full-Raster Converter Parameters 20.3. Clocked Video to Full-Raster Converter Block Description 20.4. Clocked Video Converter to Full-Raster IP Registers
20.1. About the Clocked Video to Full-Raster Converter IP x
20.1.1. Clocked Video to Full-Raster Converter Features 20.1.2. Clocked Video to Full-Raster Converter Performance and Resources
20.3. Clocked Video to Full-Raster Converter Block Description x
20.3.1. Clocked Video to Full-Raster Converter Interfaces
21. Clocked Video Output Intel® FPGA IP x
21.1. About the Clocked Video Output IP 21.2. Clocked Video Output IP Parameters 21.3. Clocked Video Output IP Functional Description 21.4. Clocked Video Output IP Interfaces 21.5. Clocked Video Output IP Registers 21.6. Clocked Video Output IP Software API
21.1. About the Clocked Video Output IP x
21.1.1. Clocked Video Output IP Performance and Resources 21.1.2. Clocked Video Output IP Features
22. Color Plane Manager Intel® FPGA IP x
22.1. About the Color Plane Manager IP 22.2. Color Plane Manager IP Parameters 22.3. Color Plane Manager IP Functional Description 22.4. Color Plane Manager IP Registers 22.5. Color Plane Manager Software API
22.1. About the Color Plane Manager IP x
22.1.1. Color Plane Manager IP Performance and Resources
22.3. Color Plane Manager IP Functional Description x
22.3.1. Color Plane Manager IP Interfaces
23. Color Space Converter Intel® FPGA IP x
23.1. About the Color Space Converter IP 23.2. Color Space Converter IP Parameters 23.3. Color Space Converter IP Functional Description 23.4. Color Space Converter IP Registers 23.5. Color Space Converter IP Software API
23.1. About the Color Space Converter IP x
23.1.1. Color Space Converter IP Features 23.1.2. Color Space Converter IP Performance and Resources
23.3. Color Space Converter IP Functional Description x
23.3.1. Color Space Converter IP Interfaces
24. Defective Pixel Correction Intel® FPGA IP x
24.1. About the Defective Pixel Correction IP 24.2. Defective Pixel Correction IP Parameters 24.3. Defective Pixel Correction IP Functional Description 24.4. Defective Pixel Correction IP Registers 24.5. Defective Pixel Correction IP Software API
24.1. About the Defective Pixel Correction IP x
24.1.1. Defective Pixel Correction IP Performance and Resources
24.3. Defective Pixel Correction IP Functional Description x
24.3.1. Defective Pixel Correction IP Interfaces
25. Deinterlacer Intel® FPGA IP x
25.1. About the Deinterlacer IP 25.2. Deinterlacer Parameters 25.3. Deinterlacer IP Functional Description 25.4. Deinterlacer IP Registers 25.5. Deinterlacer IP Software API
25.1. About the Deinterlacer IP x
25.1.1. Deinterlacer Performance and Resources
25.3. Deinterlacer IP Functional Description x
25.3.1. Deinterlacer Interfaces
26. Demosaic Intel® FPGA IP x
26.1. About the Demosaic IP 26.2. Demosaic IP Parameters 26.3. Demosaic IP Functional Description 26.4. Demosaic IP Registers 26.5. Demosaic IP Software API
26.1. About the Demosaic IP x
26.1.1. Demosaic IP Performance and Resources
26.3. Demosaic IP Functional Description x
26.3.1. Demosaic IP Interfaces
27. FIR Filter Intel® FPGA IP x
27.1. About the FIR Filter 27.2. FIR Filter Parameters 27.3. FIR Filter IP Operation 27.4. FIR Filter Interfaces 27.5. FIR Filter Registers 27.6. FIR Filter IP Software API
27.1. About the FIR Filter x
27.1.1. FIR Filter IP Performance and Resources
27.3. FIR Filter IP Operation x
27.3.1. FIR Filter Processing 27.3.2. FIR Filter Precision 27.3.3. FIR Coefficient Specification 27.3.4. FIR Filter Symmetry 27.3.5. Result to Output Data Type Conversion
27.3.4. FIR Filter Symmetry x
27.3.4.1. No Symmetry 27.3.4.2. Horizontal Symmetry 27.3.4.3. Vertical Symmetry 27.3.4.4. Horizontal and Vertical Symmetry 27.3.4.5. Diagonal Symmetry
28. Frame Cleaner Intel® FPGA IP x
28.1. About the Frame Cleaner IP 28.2. Frame Cleaner IP Parameters 28.3. Frame Cleaner IP Functional Description 28.4. Frame Cleaner IP Interfaces 28.5. Frame Cleaner IP Registers 28.6. Frame Cleaner IP Software API
28.1. About the Frame Cleaner IP x
28.1.1. Frame Cleaner IP Performance and Resources
29. Full-Raster to Clocked Video Converter Intel® FPGA IP x
29.1. About the Full-Raster to Clocked Video Converter 29.2. Full Raster to Clocked Video Converter Parameters 29.3. Full-Raster to Clocked Video Converter Block Description 29.4. Full-Raster to Clocked Video Converter Registers
29.1. About the Full-Raster to Clocked Video Converter x
29.1.1. Full-Raster to Clocked Video Converter Features 29.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
29.3. Full-Raster to Clocked Video Converter Block Description x
29.3.1. Full Raster to Clocked Video Converter Interfaces
30. Full-Raster to Streaming Converter Intel® FPGA IP x
30.1. About the Full-Raster to Streaming Converter IP 30.2. Full-Raster to Streaming Converter Parameters 30.3. Full-Raster to Streaming Converter Block Description
30.1. About the Full-Raster to Streaming Converter IP x
30.1.1. Full-Raster to Streaming Converter Features 30.1.2. Full-Raster to Streaming Converter Performance and Resources
30.3. Full-Raster to Streaming Converter Block Description x
30.3.1. Full-Raster to Streaming Converter Interfaces
31. Genlock Controller Intel® FPGA IP x
31.1. About the Genlock Controller IP 31.2. Genlock Controller IP Parameters 31.3. Genlock Controller IP Functional Description 31.4. Using Genlock Controller IP Software 31.5. Genlock Controller IP Registers 31.6. Genlock Controller IP Software API
31.1. About the Genlock Controller IP x
31.1.1. Genlock Controller IP Performance and Resources
31.3. Genlock Controller IP Functional Description x
31.3.1. Genlock Controller IP Interfaces
31.4. Using Genlock Controller IP Software x
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 31.4.3. Setting the VCXO hold over 31.4.4. Restarting the Genlock Controller IP 31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 31.4.7. Disturbing a Reference Clock (a cable pull)
32. Generic Crosspoint Intel® FPGA IP x
32.1. About the Generic Crosspoint IP 32.2. Generic Crosspoint IP Parameters 32.3. Generic Crosspoint IP Interfaces 32.4. Generic Crosspoint IP Registers 32.5. Generic Crosspoint IP Software API
32.1. About the Generic Crosspoint IP x
32.1.1. Generic Crosspoint IP Features 32.1.2. Generic Crosspoint Performance and Resources
33. Genlock Signal Router Intel® FPGA IP x
33.1. About the Genlock Signal Router IP 33.2. Genlock Signal Router IP Parameters 33.3. Genlock Signal Router IP Interfaces 33.4. Genlock Signal Router IP Registers 33.5. Genlock Signal Router IP Software API
33.1. About the Genlock Signal Router IP x
33.1.1. Genlock Signal Router IP Features 33.1.2. Genlock Signal Router IP Performance and Resources
34. Guard Bands Intel® FPGA IP x
34.1. About the Guard Bands IP 34.2. Guard Bands IP Parameters 34.3. Guard Bands IP Interfaces 34.4. Guard Bands IP Registers 34.5. Guard Bands IP Software API
34.1. About the Guard Bands IP x
34.1.1. Guard Bands IP Performance and Resources
35. Histogram Statistics Intel® FPGA IP x
35.1. About the Histogram Statistics IP 35.2. Histogram Statistics IP Parameters 35.3. Histogram Statistics IP Interfaces 35.4. Histogram Statistics IP Registers 35.5. Histogram Statistics IP Software API
35.1. About the Histogram Statistics IP x
35.1.1. Histogram Statistics IP Performance and Resources
36. Interlacer Intel® FPGA IP x
36.1. About the Interlacer IP 36.2. Interlacer IP Parameters 36.3. Interlacer IP Functional Description 36.4. Interlacer IP Registers 36.5. Interlacer IP Software API
36.1. About the Interlacer IP x
36.1.1. Interlacer IP Performance and Resources
36.3. Interlacer IP Functional Description x
36.3.1. Interlacer IP Interfaces
37. Mixer Intel® FPGA IP x
37.1. About the Mixer IP 37.2. Mixer IP Parameters 37.3. Mixer IP Functional Description 37.4. Mixer IP Registers 37.5. Mixer IP Software API
37.1. About the Mixer IP x
37.1.1. Mixer IP Performance and Resources
37.3. Mixer IP Functional Description x
37.3.1. Mixer IP Interfaces
38. Pixels in Parallel Converter Intel® FPGA IP x
38.1. About the Pixels in Parallel Converter IP 38.2. Pixels in Parallel Converter IP Parameters 38.3. Pixels in Parallel Converter Interfaces 38.4. Pixels in Parallel Converter Registers 38.5. Pixels in Parallel Converter IP Software API
38.1. About the Pixels in Parallel Converter IP x
38.1.1. Pixels in Parallel Converter IP Performance and Resources
39. Scaler Intel® FPGA IP x
39.1. About the Scaler 39.2. Scaler IP Parameters 39.3. Scaler IP Functional Description 39.4. Scaler IP Registers 39.5. Scaler IP Software API
39.1. About the Scaler x
39.1.1. Scaler IP Performance and Resources
39.2. Scaler IP Parameters x
39.2.1. Scaler Maximum Resolution
39.3. Scaler IP Functional Description x
39.3.1. Coefficient Selection 39.3.2. Coefficient Quantization 39.3.3. Filter Behavior at Edge Boundaries 39.3.4. Partial Frame Scaling 39.3.5. 422 and 420 Chroma Sampled Data Scaling 39.3.6. Scaler IP Interfaces
39.3.1. Coefficient Selection x
39.3.1.1. Updating Scaler IP Runtime Coefficients
40. Stream Cleaner Intel® FPGA IP x
40.1. About the Stream Cleaner IP 40.2. Stream Cleaner IP Parameters 40.3. Stream Cleaner IP Functional Description
40.1. About the Stream Cleaner IP x
40.1.1. Stream Cleaner IP Performance and Resources
40.3. Stream Cleaner IP Functional Description x
40.3.1. Stream Cleaner IP Interfaces
41. Switch Intel® FPGA IP x
41.1. About the Switch IP 41.2. Switch IP Parameters 41.3. Switch IP Functional Description 41.4. Switch IP Registers 41.5. Switch IP Software API
41.1. About the Switch IP x
41.1.1. Switch IP Performance and Resources
41.3. Switch IP Functional Description x
41.3.1. Switch IP Latency 41.3.2. Switch IP Interfaces
42. Tone Mapping Operator Intel® FPGA IP x
42.1. About the Tone Mapping Operator IP 42.2. TMO IP Parameters 42.3. TMO IP Block Description 42.4. TMO IP Registers 42.5. TMO IP Software API
42.1. About the Tone Mapping Operator IP x
42.1.1. TMO IP Features 42.1.2. TMO IP Performance and Resource Utilization
42.3. TMO IP Block Description x
42.3.1. TMO IP Interfaces 42.3.2. TMO IP Latency
43. Test Pattern Generator Intel® FPGA IP x
43.1. About the Test Pattern Generator IP 43.2. Test Pattern Generator IP Parameters 43.3. Test Pattern Generator IP Functional Description 43.4. Test Pattern Generator IP Registers 43.5. Test Pattern Generator IP Software API
43.1. About the Test Pattern Generator IP x
43.1.1. Test Pattern Generator IP Performance and Resources
43.3. Test Pattern Generator IP Functional Description x
43.3.1. Test Patterns 43.3.2. Output Subsampling and Color Space 43.3.3. Run-time Settings 43.3.4. Test Pattern Generator IP Interfaces
44. Unsharp Mask Intel® FPGA IP x
44.1. About the Unsharp Mask IP 44.2. Unsharp Mask IP Parameters 44.3. Unsharp Mask IP Functional Description 44.4. Unsharp Mask IP Registers 44.5. Unsharp Mask IP Software API
44.1. About the Unsharp Mask IP x
44.1.1. Unsharp Mask IP Performance and Resources
44.3. Unsharp Mask IP Functional Description x
44.3.1. Unsharp Mask IP Interfaces
45. Video and Vision Monitor Intel FPGA IP x
45.1. About the Video and Vision Monitor IP 45.2. Video and Vision Monitor IP Parameters 45.3. Video and Vision Monitor IP Functional Description 45.4. Video and Vision Monitor IP Registers 45.5. Video and Vision Monitor Software API
45.1. About the Video and Vision Monitor IP x
45.1.1. Video and Vision Monitor IP Performance and Resources
45.3. Video and Vision Monitor IP Functional Description x
45.3.1. Video and Vision Monitor IP Interfaces
46. Video Frame Buffer Intel® FPGA IP x
46.1. About the Video Frame Buffer IP 46.2. Video Frame Buffer IP Parameters 46.3. Video Frame Buffer IP Functional Description 46.4. Video Frame Buffer IP Registers 46.5. Video Frame Buffer IP Software API
46.1. About the Video Frame Buffer IP x
46.1.1. Video Frame Buffer Performance and Resources
46.3. Video Frame Buffer IP Functional Description x
46.3.1. Video Frame Buffer IP Interfaces
47. Video Frame Reader Intel FPGA IP x
47.1. About the Video Frame Reader IP 47.2. Video Frame Reader IP Parameters 47.3. Video Frame Reader IP Functional Description 47.4. Video Frame Reader IP Registers 47.5. Video Frame Reader IP Software API
47.1. About the Video Frame Reader IP x
47.1.1. Video Frame Reader IP Performance and Resources
47.3. Video Frame Reader IP Functional Description x
47.3.1. Video Frame Reader IP Interfaces
48. Video Frame Writer Intel FPGA IP x
48.1. About the Video Buffer Writer IP 48.2. Video Frame Writer IP Parameters 48.3. Video Frame Writer IP Functional Description 48.4. Video Frame Writer IP Registers 48.5. Video Frame Writer IP Software API
48.1. About the Video Buffer Writer IP x
48.1.1. Video Frame Writer IP Performance and Resources
48.3. Video Frame Writer IP Functional Description x
48.3.1. Video Frame Writer IP Interfaces
49. Video Streaming FIFO Intel® FPGA IP x
49.1. About the Video Streaming FIFO IP 49.2. Video Streaming FIFO IP Parameters 49.3. Video Streaming FIFO IP Interfaces
49.1. About the Video Streaming FIFO IP x
49.1.1. Video Streaming FIFO IP Performance and Resources
50. Video Timing Generator Intel® FPGA IP x
50.1. About the Video Timing Generator IP 50.2. Video Timing Generator IP Parameters 50.3. Video Timing Generator IP Functional Description 50.4. Video Timing Generator IP Interfaces 50.5. Video Timing Generator IP Registers 50.6. Video Timing Generator IP Software API
50.1. About the Video Timing Generator IP x
50.1.1. Video Timing Generator IP Features 50.1.2. Video Timing Generator IP Performance and Resources
51. Vignette Correction Intel® FPGA IP x
51.1. About the Vignette Correction IP 51.2. Vignette Correction IP Parameters 51.3. Vignette Correction IP Interfaces 51.4. Vignette Correction IP Registers 51.5. Vignette Correction IP Software API
51.1. About the Vignette Correction IP x
51.1.1. Vignette Correction IP Performance and Resources
52. Warp Intel® FPGA IP x
52.1. About the Warp IP 52.2. Warp IP Parameters 52.3. Warp IP Block Description 52.4. Warp IP Registers 52.5. Warp IP Software API
52.1. About the Warp IP x
52.1.1. Warp IP Features 52.1.2. Warp IP Performance and Resource Utilization
52.3. Warp IP Block Description x
52.3.1. Block Cache Tool 52.3.2. Warp IP Interfaces 52.3.3. Warp IP Latency 52.3.4. External Memory for Warp IP
52.5. Warp IP Software API x
52.5.1. Using Warp IP Software 52.5.2. Warp IP Software Code Examples
53. White Balance Correction Intel® FPGA IP x
53.1. About the White Balance Correction IP 53.2. White Balance Correction IP Parameters 53.3. White Balance Correction IP Functional Description 53.4. White Balance Correction IP Registers 53.5. White Balance Correction IP Software API
53.1. About the White Balance Correction IP x
53.1.1. White Balance Correction IP Performance and Resources
53.3. White Balance Correction IP Functional Description x
53.3.1. White Balance Correction IP Interfaces
54. White Balance Statistics Intel® FPGA IP x
54.1. About the White Balance Statistics IP 54.2. White Balance Statistics IP Parameters 54.3. White Balance Statistics IP Interfaces 54.4. White Balance Statistics IP Registers 54.5. White Balance Statistics IP Software API
54.1. About the White Balance Statistics IP x
54.1.1. White Balance Statistics IP Performance and Resources
55. Design Security x
55.1. Memory Subsystems 55.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Tone Mapping Operator Intel® FPGA IP
43. Test Pattern Generator Intel® FPGA IP
44. Unsharp Mask Intel® FPGA IP
45. Video and Vision Monitor Intel FPGA IP
46. Video Frame Buffer Intel® FPGA IP
47. Video Frame Reader Intel FPGA IP
48. Video Frame Writer Intel FPGA IP
49. Video Streaming FIFO Intel® FPGA IP
50. Video Timing Generator Intel® FPGA IP
51. Vignette Correction Intel® FPGA IP
52. Warp Intel® FPGA IP
53. White Balance Correction Intel® FPGA IP
54. White Balance Statistics Intel® FPGA IP
55. Design Security
56. Document Revision History for Video and Vision Processing Suite User Guide

11.4. Advanced Test Pattern Generator IP Registers

Each register is either read-only (RO) or read-write (RW). If Debug features is off, all RW registers are write-only (WO).
Table 77.  Advanced Test Pattern Generator IP General Registers
Address Register Access Description
Parameterization registers
0x0000 VID_PID RO

Read this register to retrieve the Advanced test pattern generator product ID.

This register always returns 0x6AF7_0252.

0x0004 VERSION RO Read this register to retrieve the version information for the Quartus release that Altera uses to build the IP.
0x0008 LITE_MODE RO Read this register to determine if lite mode is on. This register returns 0 for Full mode and 1 for Lite mode.
0x000C DEBUG_ENABLED RO

Read this register to determine if Debug features is on.

This register returns 1 if reads to other registers designated as RW return the last value you write to the register, or an undefined value.

0x0010 NUM_PATTERNS RO Read this register to determine the number of test pattern configurations
0x0014 BPS RO Read this register to determine the number of bits per color plane
0x0018 PIXELS_IN_PARALLEL RO Read this register to determine the number of pixels transmitted per clock cycle at the streaming output
0x001C COLOR_SPACE RO Read this register to determine the color space and chroma sampling. This register returns:
  • 0 for RGB
  • 1 for YCbCr 4:4:4
  • 2 for YCbCr 4:2:2
  • 3 for YCbCr 4:2:0
  • 4 for monochrome
0x00210 PATTERN_0_TYPE RO Read this register to determine the pattern type of test pattern configuration 0. This register returns:
  • 0 for the bars pattern
  • 1 for constant color
  • 2 for SDI pathological
  • 3 for zone plate
  • 4 for digital clock
0x0024 PATTERN_1_TYPE RO Read this register to determine the pattern type of test pattern configuration 1. This register returns:
  • 0 for the bars pattern
  • 1 for constant color
  • 2 for SDI pathological
  • 3 for zone plate
  • 4 for digital clock
0x002C PATTERN_2_TYPE RO Read this register to determine the pattern type of test pattern configuration 2. This register returns:
  • 0 for the bars pattern
  • 1 for constant color
  • 2 for SDI pathological
  • 3 for zone plate
  • 4 for digital clock
0x002C PATTERN_3_TYPE RO Read this register to determine the pattern type of test pattern configuration 3. This register returns:
  • 0 for the bars pattern
  • 1 for constant color
  • 2 for SDI pathological
  • 3 for zone plate
  • 4 for digital clock
0x0030 PATTERN_4_TYPE RO Read this register to determine the pattern type of test pattern configuration 4. This register returns:
  • 0 for the bars pattern
  • 1 for constant color
  • 2 for SDI pathological
  • 3 for zone plate
  • 4 for digital clock
0x0034 PATTERN_5_TYPE RO Read this register to determine the pattern type of test pattern configuration 5. This register returns:
  • 0 for the bars pattern
  • 1 for constant color
  • 2 for SDI pathological
  • 3 for zone plate
  • 4 for digital clock
0x0038 PATTERN_6_TYPE RO Read this register to determine the pattern type of test pattern configuration 6. This register returns:
  • 0 for the bars pattern
  • 1 for constant color
  • 2 for SDI pathological
  • 3 for zone plate
  • 4 for digital clock
0x003C PATTERN_7_TYPE RO Read this register to determine the pattern type of test pattern configuration 7. This register returns:
  • 0 for the bars pattern
  • 1 for constant color
  • 2 for SDI pathological
  • 3 for zone plate
  • 4 for digital clock
0x0040 to 0x013C unused
0x0140 STATUS RO

Bit 0: Status bit.

1 = advanced test pattern generator is processing a video field, 0 otherwise.

Bit 1 : Pending register updates bit

Lite mode is off only.

Any writes to registers excluding pattern X registers cause the IP to raise pending register updates bit, to indicate outstanding changes yet to be committed. Refer to register Pattern X Select for more information.

The IP lowers this bit at the next field boundary after a write to the COMMIT register.

0x0144 FIELD_COUNT RO Read this register to determine the output field count. The value in this register is reset each time the IP stops.
0x0148 CONTROL RW

Bit 0: Go bit.

Write 0 to this register to stop the test pattern generator at the end of the current frame. Write 1 to this register to start or restart output generation. This register initializes to 0 at start-up and no output fields are generated until after a write of 1 to this register.

Writes to this register apply immediately, without needing to further write to COMMIT.

0x014C COMMIT RW The IP holds any changes pending to registers (excluding those prefixed with PATTERN_X_) until you send a write to this register. The value you write is unimportant.
0x0150 FIELD_WIDTH RW

Write to this register to set the width of outgoing video fields. If the output chroma sampling is 4:2:2 or 4:2:0, the width should be a multiple of 2.

The width of the canvas that applies to pattern 0. If the widths and offsets of other patterns (set via LAYER_N registers) cause that pattern to go out of the canvas boundaries, the IP does not show that pattern.

0x0154 FIELD_HEIGHT RW

Use this register to set the height for outgoing video fields. If the output chroma subsampling is 4:2:0, the height should be a multiple of 2.

The height of the canvas that applies to pattern 0. If the height and offsets of other patterns (set via LAYER_N registers) cause that pattern to go out of the canvas boundaries, the IP does not shows that pattern.

0x0158 FIELD_INTERLACE RW

Use this register to set the interlace output behavior for the first outgoing field. The value you write corresponds to the interlace identifier nibble of outgoing image information packets in full mode.

Values 0 to 7 produce progressive outputs.

Values 8 to 1 cause the field sequence to restart with F0.

Values 12 to 15 cause the field sequence to restart with F1.
0x015C + (n-1) *0x14 LAYER_N_WIDTH RW

Use this register to set the width of layer or pattern n (excluding pattern 0).

23
0x0160 + (n-1) *0x14 LAYER_N_HEIGHT RW

Use this register to set the height of layer or pattern n (excluding pattern 0).

23
0x0164 + (n-1) *0x14 LAYER_N_ALPHA RW Use this register to set the alpha value of layer or pattern n (excluding pattern 0). .
0x0168 + (n-1) *0x14 LAYER_N_H_OFFSET RW

Use this register to set the horizontal offset of layer or pattern n (excluding pattern 0).

23
0x016C + (n-1) *0x14 LAYER_N_V_OFFSET RW

Use this register to set the vertical offset of layer/pattern n (excluding pattern 0).

23
0x01E8 PATTERN_X_SELECT RW

Write to this register with values 0 to 7 to apply all pattern X registers to the given pattern number.

Only the registers that apply to the selected pattern have an effect.

Pattern configuration registers

The following sets of registers have different semantics according to the different types of test patterns, and they may share addresses. When you write a pattern number “X” to PATTERN_X_SELECT, only the registers that correspond to the test pattern type of pattern X have an effect.

Ensure you write to all registers specific for a type of pattern before committing via PATTERN_X_SELECT; values from previous writes may persist in registers otherwise, leading to unwanted behavior.

Table 78.  Advanced Test Pattern Generator IP Bars Pattern Registers
Address Register Access Description 24
0x01EC PATTERN_X_BARS_SELECT WO

Write to this register to set the variant of the bars pattern to use. Write: .

  • 0 for color bars
  • 1 for greyscale bars
  • 2 for black and white bars
  • 3 for mixed bars
Table 79.   Advanced Test Pattern Generator IP Constant color pattern registers
Address Register Access Description 25
0x01EC PATTERN_X_CONST_C0

WO

Write to this register to set the value for color plane 0 (B or Cb) by the constant color test pattern.

0x01F0 PATTERN_X_CONST_C1 WO

Write to this register to set the value for color plane 1 (G or Y) by the constant color test pattern.

0x01F4 PATTERN_X_CONST_C2 WO

Write to this register to set the value for color plane 2 (R or Cr) by the constant color test pattern.

Table 80.   Advanced Test Pattern Generator IP Zone plate pattern registers
Address Register Access Description 26
0x01EC PATTERN_X_ZONE_X_ORIGIN

WO

Write to this register to set the X coordinate of the zone plate center (origin). For example, write 960 to horizontally set the centre of the zone plate to the middle of a 1920x1080 display.

0x01F0 PATTERN_X_ZONE_Y_ORIGIN

WO

Write to this register to set the Y coordinate of the zone plate center (origin). For example, write 540 to vertically set the centre of the zone plate to the middle of a 1920x1080 display.

0x01F4 PATTERN_X_ZONE_COARSE_FACTOR

WO

This value is a rough scale up or down of the zone plate. The bigger the value, the more zoomed in the zone plate is.

This value is arbitrary, but start with a value of 14 on 1920x1080, and 20 on a 4k display.

0x01F8 PATTERN_X_ZONE_FINE_FACTOR

WO

The value of this register acts as a fine tune scaling factor of the zone plate.

It is a 16-bit unsigned fixed-point number, with 8 bits fractional part.

The IP implements this value as a constant k in f(kx) (applied after ZONE_POWER_FACTOR). The bigger the value, the more zoomed out the zone plate is.

Table 81.  Advanced Test Pattern Generator IP Digital clock pattern registers
Address Register Access Description 27
0x01EC PATTERN_X_DIGITAL_CONFIGURATION

WO

 Bit 0: write 1 to pause the digital clock, 0 to resume.

Bit 1: write 1 to reset the clock to 00:00:00,00; write 0 to resume.

0x01F0 PATTERN_X_DIGITAL_BACKGROUND_B

WO

Write to this register to set the value for color plane 0 (B or Cb), which is the background color for the digital clock pattern.

0x01F4 PATTERN_X_DIGITAL_BACKGROUND_G

WO

Write to this register to set the value for color plane 1 (G or Y), which is the background color for the digital clock pattern.

0x01F8 PATTERN_X_DIGITAL_BACKGROUND_R

WO

Write to this register to set the value for color plane 2 (B or Y), which is the background color for the digital clock pattern.

0x01FC PATTERN_X_DIGITAL_FONT_B

WO

Write to this register to set the value for color plane 0 (B or Cb), which is the font color for the digital clock pattern.

0x0200 PATTERN_X_DIGITAL_FONT_G

WO

Write to this register to set the value for color plane 1 (G or Y), which is the font color for the digital clock pattern.

0x0204 PATTERN_X_DIGITAL_FONT_R

WO

Write to this register to set the value for color plane 2 (B or Y) used as the font color for the digital clock pattern.

0x0208 PATTERN_X_DIGITAL_LOCATION_X WO

Write to this register to set the X coordinate of the top-left pixel of the digital clock test pattern.

0x020C PATTERN_X_DIGITAL_LOCATION_Y WO

Write to this register to set the Y coordinate of the top-left pixel of the digital clock test pattern.

0x0210 PATTERN_X_DIGITAL_SCALE_FACTOR WO

Write to this register to set the scaling factor of the digital clock. When 1, each character of the display is 8x8 pixels; in total 88x8 pixels.

0x0214 PATTERN_X_DIGITAL_FPS WO

Write to this register to set the FPS that the digital clock; uses. Determines how many frames before a second passes. Does not effect on actual video refresh rate.

Register Bit Description

Table 82.  VID_PID
Name Bits Description
Advanced test pattern generator version ID and product ID 31:0

This register always returns 0x6AF7_0252.

  • 15:0 is the product ID and always returns 0x0252
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 83.  VERSION
Name Bits Description
Register map version 7:0 Register map version. Returns 0x01.
QPDS patch revision 15:8 This returns 0x00
QPDS update revision 23:16 Updated for each release. For 24.2 this returns 0x02.
QPDS major revision 31:24 Updated for each release. For 24.2 this returns 0x18.

Table 84.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 31:0 Returns 1 if Lite mode is on and 0 otherwise
Table 85.  DEBUG_ENABLED
Name Bits Description
Lite mode parameterization bit 31:0 Returns 1 if Debug features is on and 0 otherwise
Table 86.   NUM_PATTERNS
Name Bits Description
Number of enabled patterns 31:0 Returns the number of enabled test patterns
Table 87.  BPS
Name Bits Description
Bits per color sample 31:0 Returns the number of bits per color sample
Table 88.  PIXELS_IN_PARALLEL
Name Bits Description
Lite mode parameterization bit 31:0 Returns the number of pixels processed per clock cycle
Table 89.  COLOR_SPACE
Name Bits Description
Color space and subsampling 31:0

Returns:

  • 0 for RGB
  • 1 for YCbCr 4:4:4
  • 2 for YCbCr 4:2:2
  • 3 for YCbCr 4:2:0
  • 4 for monochrome
Table 90.  PATTERN_X_TYPE
Name Bits Description
Pattern type for pattern number X 31:0

Returns the pattern type of pattern number X:

  • 0 for bars pattern
  • 1 for constant color pattern
  • 2 for SDI pathological pattern
  • 3 for zone plate pattern
  • 4 for digital clock pattern
Table 91.  STATUS
Name Bits Description
Processing video status bit 0 Returns 1 if the IP is currently processing a video field; 0 otherwise
Pending register updates bit 1 Returns 1 if the IP has pending updates to any writable registers excluding pattern configuration registers (prefixed with PATTERN_X_)
Unused 31:2 Unused
Table 92.  FIELD_COUNT
Name Bits Description
Field count 15:0 Returns the number of fields or frames the IP generates since it last started.
Unused 31:16 Unused
Table 93.  CONTROL
Name Bits Description
Go bit 0 Write 1 to start the IP. Write 0 to stop the IP as soon as it has finishes generating the current frame.
Unused 31:1 Unused
Table 94.  COMMIT
Name Bits Description
Unused 31:0 Unused. (The value you write value is unimportant).
Table 95.  FIELD_WIDTH
Name Bits Description
Field/frame width 16:0 Set the width (in pixels) of outgoing fields.
Unused 31:17 Unused.
Table 96.  FIELD_HEIGHT
Name Bits Description
Field/frame height 16:0 Set the height (in pixels) of outgoing fields.
Unused 31:17 Unused.
Table 97.  FIELD_INTERLACE
Name Bits Description
Field/frame width 3:0 Set the interlace configuration for outgoing fields.
Unused 31:4 Unused.
Table 98.  LAYER_N_WIDTH
Name Bits Description
Layer n field width 16:0 Field width for layer n. LAYER_N_WIDTH where n >= NUM_PATTERNS has no effect.
Unused 31:17 Unused
Table 99.  LAYER_N_HEIGHT
Name Bits Description
Layer n field height 16:0 Field height for layer n. LAYER_N_WIDTH where n >= NUM_PATTERNS has no effect.
Unused 31:17 Unused
Table 100.  LAYER_N_ALPHA
Name Bits Description
Layer n alpha (Bits per color sample – 1):0 Alpha value for layer n. LAYER_N_WIDTH where n >= NUM_PATTERNS has no effect.
Unused 31:(Bits per color sample) Unused
Table 101.  LAYER_N_H_OFFSET
Name Bits Description
Layer n horizontal offset 16:0 Horizontal offset for layer n. LAYER_N_WIDTH where n >= NUM_PATTERNS has no effect.
Unused 31:17 Unused
Table 102.  LAYER_N_V_OFFSET
Name Bits Description
Layer n vertical offset 16:0 Vertical offset for layer n. LAYER_N_WIDTH where n >= NUM_PATTERNS has no effect.
Unused 31:17 Unused
Table 103.   PATTERN_X_SELECT
Name Bits Description
Pattern number 2:0

Write the pattern number (0-7) you want to apply all PATTERN_X settings to.

Any write to PATTERN_X registers are pending until you write to this register.

Only the relevant registers to a given pattern applies, i.e. PATTERN_X_ZONE_FINE_FACTOR only applies to pattern numbers corresponding to a zone plate test pattern and ignored for all others.

Unused 31:3 Unused
Table 104.  PATTERN_X_CONST_C0/1/2
Name Bits Description
Color value (BPS – 1):0 Constant color value for color plane 0/1/2 for pattern number X.
Unused 31:BPS Unused
Table 105.  PATTERN_X_BARS_SELECT
Name Bits Description
Bars mode select 1:0 0 = color bars, 1 = greyscale bars, 2 = black and white bars, 3 = mixed bars for pattern number X.
Unused 31:2 Unused

Table 106.  PATTERN_X_ZONE_X/Y_ORIGIN
Name Bits Description
Origin X/Y 15:0 Sets x/y part of center coordinates of zone plate for pattern number X.
Unused 31:16 Unused
Table 107.  PATTERN_X_ZONE_COARSE_FACTOR
Name Bits Description
Coarse scaling factor 4:0 Arbitrary sizing factor (same as scaling factor above). Increase factor to increase zone plate size coarsely (downshifts k in f(kx) so increased size). This value applies to pattern number X.
Unused 31:5 Unused
Table 108.  PATTERN_X_ZONE_FINE_FACTOR
Name Bits Description
Fine tune scaling factor 15:0 Fixed point operand, with 8 bits fractional part. Increase factor to decrease zone plate size smoothly (increase k in f(kx) hence decreased size). This value applies to pattern number X.
Unused 31:16 Unused
Table 109.  PATTERN_X_DIGITAL_CONFIGURATION
Name Bits Description
Pause 0 Write 1 to pause the digital clock display at its currently displayed time for pattern number X. Write 0 to resume the digital clock display for pattern number X.
Soft reset 1

Write 1 to reset and hold the digital clock display at 00:00:00,00. Write 0 to resume the digital clock display for pattern number X.

This value takes precedence over pause, so even if pause is set to 0 the display remains locked until you write 0 to this register. Similarly, if the display is paused, writing 1 to this register resets it to 00:00:00,00.

Unused 31:2 Unused
Table 110.  PATTERN_X_DIGITAL_BACKGROUND_B/G/R
Name Bits Description
Background color value 15:0 Sets B/G/R or Cb/Y/Cr component of the background color of the digital clock for pattern number X.
Unused 31:16 Unused
Table 111.  PATTERN_X_DIGITAL_FONT_B/G/R
Name Bits Description
Font color value 15:0 Sets B/G/R or Cb/Y/Cr component of the font color of the digital clock for pattern number X.
Unused 31:16 Unused
Table 112.  PATTERN_X_DIGITAL_LOCATION_X/Y
Name Bits Description
Location X/Y 15:0 Sets the X/Y coordinate of the digital clock for Pattern number X
Unused 31:16 Unused
Table 113.  PATTERN_X_DIGITAL_SCALE_FACTOR
Name Bits Description
Scale factor 10:0 Sets the scaling multiplier of the digital clock display.
Unused 31:11 Unused
Table 114.  PATTERN_X_DIGITAL_FPS
Name Bits Description
Scale factor 5:0 Sets the FPS that determines after how many frames a second passes for the digital clock display.
Unused 31:16 Unused
23 If the dimensions and offsets of layer n cause pattern n to cross the canvas boundaries, the IP does not shows the pattern.
24 The IP ignores the value in this register for pattern X if it does not use the bars pattern.
25 The IP ignores the value in this register for pattern X if it does not use the constant color test pattern.
26 The IP ignores the value in this register for pattern X if it does not use the zone plate pattern.
27

The IP ignores the value in this register for pattern X if it does not use the digital clock pattern.

Level Two Title