Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

22.4. Color Plane Manager IP Registers

Each register is either read-only (RO) or read-write (RW).
Note: The register map is only available when you select rearrange for Color plane manager mode. When you select split or merge, the IP has no memory mapped control interface.

Table 351.   Color Plane Manager IP Registers In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_COLOR PLANE MANAGER as appropriate and with an optional REG suffix
Address Register Access Description
Parameterization registers
0x0000 VID_PID RO Read this register for the color plane manager product ID. This register always returns 0x6AF7_023B.
0x0004 VERSION RO Read this register for the IP version information
0x0008 LITE_MODE RO This register returns 1 if you select Lite Mode for the IP.
0x000C DEBUG_ENABLED RO Read this register to determine if debug features are on.
0x0010 BITS_PER_SYMBOL RO Read this register for bits per symbol configuration information.
0x0014 PIXELS_IN_PARALLEL RO Read this register for pixels in parallel configuration information.
0x0018 NUMBER_OF_INPUT_COLOR_PLANES RO Read this register for input color plane configuration information.
0x001C NUMBER_OF_OUTPUT_COLOR_PLANES RO Read this register for output color plane configuration information.
0x0020 MAPPING_FOR_OUTPUT_COLOR_PLANE0 RO Read this register for color plane 0 mapping information.
0x0024 MAPPING_FOR_OUTPUT_COLOR_PLANE1 RO Read this register for color plane 1 mapping information.
0x0028 MAPPING_FOR_OUTPUT_COLOR_PLANE2 RO Read this register for color plane 2 mapping information.
0x002C MAPPING_FOR_OUTPUT_COLOR_PLANE3 RO Read this register for color plane 3 mapping information.

0x0030 to

0x011F

Reserved

Control and Debug registers

0x0120 IMG_INFO_WIDTH RO The expected width of the incoming video fields. For full designs, the received width in the IP derives from the image information packets.
0x0124 IMG_INFO_HEIGHT RO The expected height of the incoming video fields. For full designs, the received height in the IP derives from the image information packets.
0x0128 IMG_INFO_INTERLACE RO The expected interlace information of the incoming video fields. For full designs, the received interlace information in image information packets.
0x012C RESERVED RO Unused.
0x0130 IMG_INFO_COLORSPACE RO The expected color space of the incoming video fields. For full designs, the received color space in image information packets.
0x0134 IMG_INFO_SUBSAMPLING RO The expected chroma subsampling of the incoming video fields. For full designs, the received chroma subsampling in image information packets.
0x0138 IMG_INFO_COSITING RO The expected chroma co-siting of theincoming video fields. For full designs, the received chroma co-siting in image information packets.
0x013C IMG_INFO_FIELD_COUNT RO The received field count field in image information packets.
0x0140 STATUS RO

Bit 0: status bit.

Bit 1: Pending writes bit.

0x0144 COMMIT RW Write 1 to bit 0 to commit the color plane padding values.
0x0148 COLOR_PLANE_0_PAD RW Color plane 0 dynamic padding value.
0x014C COLOR_PLANE_1_PAD RW Color plane 1 dynamic padding value.
0x0150 COLOR_PLANE_2_PAD RW Color plane 2 dynamic padding value.
0x0154 COLOR_PLANE_3_PAD RW Color plane 3 dynamic padding value.

Register Bit Descriptions

Note: The register map is only available when you select rearrange for color plane manager. When you select split or merge, the IP has no memory mapped control interface.
Table 352.   VID_PID
Name Bits Description
Color plane manager version ID and product ID 31:0

This register always returns 0x6AF7_023B

  • 15:0 is the product ID and always returns 0x023B
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 353.  VERSION
Name Bits Description
Register map version 7:0 Register map version.
IP patch revision 15:8 -
IP update revision 23:16 Updated when the IP version changes.
IP major revision 31:24 Updated when the IP version changes.
Table 354.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on Lite mode.
Unused 31:1 Unused.
Table 355.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 356.  BITS_PER_SYMBOL
Name Bits Description
Bits per symbol 31:0

Read this register for bits per symbol configuration information.

Table 357.  PIXELS_IN_PARALLEL
Name Bits Description
Number of pixels in parallel 31:0

Read this register for pixels in parallel configuration information.

Table 358.  NUMBER_OF_INPUT_COLOR_PLANES
Name Bits Description
Number of input color planes 31:0

Read this register for number of input color planes configuration information.

Table 359.  NUMBER_OF_OUTPUT_COLOR_PLANES
Name Bits Description
Number of output color planes 31:0

Read this register for number of output color planes configuration information.

Table 360.  MAPPING_FOR_OUTPUT_COLOR_PLANE0
Name Bits Description
Mapping for output color plane 0 31:0

Read this register for the output color plane 0 mapping information.

  • 0 = Input color plane 0
  • 1 = Input color plane 1
  • 2 = Input color plane 2
  • 3 = Input color plane 3
  • 4 = Padding
Table 361.  MAPPING_FOR_OUTPUT_COLOR_PLANE1
Name Bits Description
Mapping for output color plane 1 31:0

Read this register for the output color plane 1 mapping information.

  • 0 = Input color plane 0
  • 1 = Input color plane 1
  • 2 = Input color plane 2
  • 3 = Input color plane 3
  • 4 = Padding
Table 362.  MAPPING_FOR_OUTPUT_COLOR_PLANE2
Name Bits Description
Mapping for output color plane 2 31:0

Read this register for the output color plane 2 mapping information.

  • 0 = Input color plane 0
  • 1 = Input color plane 1
  • 2 = Input color plane 2
  • 3 = Input color plane 3
  • 4 = Padding
Table 363.  MAPPING_FOR_OUTPUT_COLOR_PLANE3
Name Bits Description
Mapping for output color plane 3 31:0

Read this register for the output color plane 3 mapping information.

  • 0 = Input color plane 0
  • 1 = Input color plane 1
  • 2 = Input color plane 2
  • 3 = Input color plane 3
  • 4 = Padding
Table 364.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

When you turn off lite mode and turn on Debug features, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 365.  IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

When you turn off lite mode and turn on Debug features, this register returns the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 366.  IMG_INFO_INTERLACE
Name Bits Description
InterlaceNibble bits 3:0

Whenyou turn off lite mode and turn on Debug features, this register returns the intlaceNibble field from the most recently received image information packet.

unused 31:4 Unused.
Table 367.  IMG_INFO_COLORSPACE
Name Bits Description
CSPcode bits 6:0

When you turn off lite mode and turn on Debug features, this register returns color space information from the most recently received image information packet.

unused 31:7 Unused.
Table 368.  IMG_INFO_SUBSAMPLING
Name Bits Description
CSPSubSacode bits 1:0

When you turn off lite mode and turn on Debug features, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 369.   IMG_INFO_COSITING
Name Bits Description
Cositecode bits 1:0

When you turn off lite mode and turn on Debug features, this register returns the COSITE field from the most recently received image information packet.

unused 31:2 Unused.
Table 370.  IMG_INFO_FIELD_COUNT
Name Bits Description
Countbits 6:0

When you turn on lite mode, this register has no function.

When you turn off lite mode and turn on Debug features, this register returns the 7 bit FIELD_COUNT field from the most recently received imageinformation packet.

unused 31:7 Unused.
Table 371.  STATUS
Name Bit Description
Status 0 The status bit is set if the IP is producing a frame. It returns to 0 in between frames.
Pending writes 1 The pending writes bit is set after a write to:
  • COLOR_PLANE0_PAD
  • COLOR_PLANE1_PAD
  • COLOR_PLANE2_PAD
  • COLOR_PLANE3_PAD
Table 372.  COMMIT
Name Bit Description
Commit 0 Write this register to commit new padding values. The values take effect at the start of frame.
Table 373.  COLOR_PLANE0_PAD
Name Bits Description
Dynamic padding value for output color plane 0 31:0 Write this register to set the output color plane 0 dynamic padding information. If MAPPING_FOR_OUTPUT_COLOR_PLANE0 is not set to 4 (padding), this register has no effect. Write to the COMMIT register for the new padding values to take effect at the next frame.
Table 374.  COLOR_PLANE1_PAD
Name Bits Description
Dynamic padding value for output color plane 1 31:0 Write this register to set the output color plane 1 dynamic padding information. If MAPPING_FOR_OUTPUT_COLOR_PLANE1 is not set to 4 (padding), this register has no effect. Write to the COMMIT register for the new padding values to take effect at the next frame.
Table 375.  COLOR_PLANE2_PAD
Name Bits Description
Dynamic padding value for output color plane 2 31:0 Write this register to set the output color plane 2 dynamic padding information. If MAPPING_FOR_OUTPUT_COLOR_PLANE2 is not set to 4 (padding), this register has no effect. Write to the COMMIT register for the new padding values to take effect at the next frame.
Table 376.  COLOR_PLANE3_PAD
Name Bits Description
Dynamic padding value for output color plane 3 31:0 Write this register to set the output color plane 3 dynamic padding information. If MAPPING_FOR_OUTPUT_COLOR_PLANE3 is not set to 4 (padding), this register has no effect. Write to the COMMIT register for the new padding values to take effect at the next frame.