Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

10.4. Adaptive Noise Reduction IP Registers

Each register is either read-only (RO), read-write (RW) or write-only (WO).
Table 67.  Adaptive Noise Reduction IP RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_ANR as appropriate and with an optional REG suffix.
Address Register Access Description
Lite 13 Full
Parameterization registers
0x0000 VID_PID RO N/A

Read this register to retrieve the ID of the IP.

This register always returns 0x6FA7_0176.

0x0004 VERSION RO N/A Read this register to retrieve the version information for the IP.
0x0008 LITE_MODE RO N/A

Read this register to determine if lite mode is on.

This register always returns 1.

0x000C DEBUG_ENABLED RO N/A

Read this register to determine if debug features are on.

This register returns 0 for off and 1 for on.

0x0010 BPS_IN RO N/A Read this register to determine the bits per symbol for the input data.
0x0014 BPS_OUT RO N/A Read this register to determine the bits per symbol for the output data.
0x0018 NUM_COLOR RO N/A Read this register to determine the number of color planes.
0x001C CFA_ENABLED RO N/A Read this register to determine if enable CFA is on.
0x0020 PIP RO N/A Read this register to determine the number of pixels in parallel.
0x0024 MAX_WIDTH RO N/A Read this register to determine the maximum supported input field width.
0x0028 H_TAPS RO N/A Read this register to determine the number of horizontal taps
0x002C V_TAPS RO N/A Read this register to determine the number of vertical taps
0x0030 to 0x011F - - - Reserved
Control, debug and statistics registers
0x0120 IMG_INFO_WIDTH RW N/A The expected width of the incoming video fields.
0x0124 IMG_INFO_HEIGHT RW N/A The expected height of the incoming video fields.
0x0128 to 0x013F - - - Reserved
0x0140 STATUS RO N/A

Read this register for information about the Adaptive Noise Reduction IP status.

  • [0]: Running
  • [31:1]: Reserved
0x0144 FRAME_STATS RO N/A

Read this register for some frame statistics.

  • [7:0]: A simple checksum of the frame
  • [31:8]: Reserved
0x0148 COMMIT RW N/A Write any value to this register to submit changes to the control register, and intensity range, and spatial distance lookup tables.
0x014c CONTROL RW N/A

Control bits and fields of Adaptive Noise Reduction IP

  • [0]: Bypass bit. When set Adaptive Noise Reduction IP passes input pixel values untouched.
  • [31:1]: Reserved
0x0150 to 0x01FF - - - Reserved
0x0200 to 0x11FF INTENSITY_LUT[k] 14 WO N/A

Intensity range lookup table entries.

  • [19:0]: Lookup value
  • [31:20]: Reserved

0x1200

to

0x1200 + 4 x SPATIAL_LUT_DEPTH 15 - 1

SPATIAL_LUT[i] 16 RW N/A

Spatial distance lookup table entries.

  • [19:0]: Lookup value
  • [31:20]: Reserved

0x1200 + 4 x SPATIAL_LUT_DEPTH

to

0x1FFF

- - - Not implemented

Register Bit Descriptions

Table 68.   STATUS
Name Bits Description
Reserved 31:1 Reserved.
Running 0 When 1, the IP processes data.
Table 69.   FRAME_STATS
Name Bits Description
Reserved 31:8 Reserved.
Checksum 7:0 A simple checksum of the frame.
Table 70.   CONTROL
Name Bits Description
Reserved 31:1 Reserved
Bypass 0 Set to bypass adaptive noise reduction. When set, adaptive noise reduction passes pixel values unprocessed.
13

Registers are RW only if you also turn on Debug features, otherwise they are WO.

14 Index k from 0 to 1023
15 If Enable CFA is off SPATIAL_LUT_DEPTH = (H_TAPS - 1) / 2 + (V_TAPS - 1) / 2

if Enable CFA is on SPATIAL_LUT_DEPTH = (H_TAPS - 1) / 4 + (V_TAPS - 1) / 4

16 Index i from 0 to SPATIAL_LUT_DEPTH - 1