Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide
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49.5.2. Warp IP Software Code Examples

UHD 60 Hz Workflow example

This example shows the workflow and basic warp software usage of the C++ source code to generate and apply 15 degree rotation warp. The example is for 3840x2160@60Hz video, which requires the processing to be split between two warp engines. The frame buffer and warp coefficient base addresses in the example are arbitrary. Actual values depend on a particular system design.

const uint32_t FRAMEBUF_BASE_ADDR	= 0x80000000;
const uint32_t COEF_BASE_ADDR		= 0xa0000000;
const uint32_t SKIP_RAM_PAGE		= 0;
intel_vvp_warp_base_t base			= INTEL_VVP_WARP_BASE;
intel_vvp_warp_instance_t wrp0;

// Initialize driver instance
intel_vvp_warp_init_instance(&wrp0, base);

// Create warp channel
intel_vvp_warp_channel_t* ch0 = intel_vvp_warp_create_double_channel(&wrp0, 0, 0, 1, 0);

// Fill in warp channel configuration structure
intel_vvp_warp_channel_config_t cfg;
cfg.ram_addr = FRAMEBUF_BASE_ADDR;	// Frame buffers base address
cfg.cs = ERGB_FULL;					// Video colourspace
cfg.width_input = 3840;				// Video dimensions 
cfg.height_input = 2160;
cfg.width_output = 3840;
cfg.height_output = 2160;
cfg.lfr = 0;						// No low frame rate fallback

// Configure warp channel using the parameters above
intel_vvp_warp_configure_channel(ch0, &cfg);

// Obtain required hardware information
WarpHwContextPtr hw = WarpDataHelper::GetHwContext(ch0);

// Instantiate and initialize mesh generator
WarpConfigurator configurator{ hw };
configurator.SetInputResolution(3840, 2160);
configurator.SetOutputResolution(3840, 2160);

// Generate mesh
WarpMeshPtr mesh = configurator.GenerateMeshFromFixed();
WarpMeshSet mesh_set{ mesh };

// Instantiate data generator
WarpDataGenerator data_generator;

WarpDataContext ctx{ hw,
	3840, 2160,
	3840, 2160

// Generate warp data using provided hardware configuration and mesh
WarpDataPtr user_data = data_generator.GenerateData(ctx, mesh_set);

// Allocate and fill in intel_vvp_warp_data_t object required by the warp driver
WarpDataHelper::WarpDriverDataPtr driver_data =
WarpDataHelper::GenerateDriverData(ctx, user_data, COEF_BASE_ADDR, SKIP_RAM_PAGE);

// Transfer generated warp data to the calculated destination for each engine
for(uint32_t i = 0; i < driver_data->num_engines; ++i)
	const WarpEngineData* ue = user_data->GetEngineData(i);
	intel_vvp_warp_engine_data_t* de = &(driver_data->engine_data[i]);
	memcpy((void*)(de->mesh_addr), ue->GetMeshData(), de->mesh_size);
	memcpy((void*)(de->filter_addr),ue->GetFilterData(), de->filter_size);
	memcpy((void*)(de->fetch_addr), ue->GetFetchData(), de->fetch_size);

// Apply warp by passing new warp data set to the driver
intel_vvp_warp_apply_transform(ch0, driver_data.get());

// Release allocated resources

Warp mesh usage

Define required warp using the WarpMesh object. The example shows the simplest case of 1:1 (unity) warp for a 3840x2160 video.

intel_vvp_warp::WarpMesh mesh{3840, 2160};

for(uint32_t v = 0; v < mesh.GetVNodes(); ++v)
	mesh_node_t* node = mesh.GetRow(v);

	for(uint32_t h = 0; h < mesh.GetHNodes(); ++h)
					  node->_x = (h * mesh.GetStep()) << 4;
		  node->_y = (v * mesh.GetStep()) << 4;

Mesh coordinates use the least significant four bits as fractional part for subpixel precision. In the example above the fractional part is always 0. Store subpixel positions in the following way:

mesh_node_t* node = mesh.GetRow(v);
float pos_x = 10.6f;
node->_x = static_cast<int32_t>(roundf(pos_x * 16.0f));

Easy warp example

When you turn on Easy warp you can rotate the input video to 0, 90, 180 or 270 degrees or mirror the video without the need of transform mesh and associated warp data.

const uint32_t FRAMEBUF_BASE_ADDR	= 0x80000000;
const uint32_t width			= 1920;
const uint32_t height			= 1080;
intel_vvp_warp_base_t base		= INTEL_VVP_WARP_BASE;
intel_vvp_warp_instance wrp0;

// Initialize driver instance
intel_vvp_warp_init_instance(&wrp0, base);

// Allocate Easy warp channel
intel_vvp_warp_channel_t* ch0 = intel_vvp_warp_create_easy_warp_channel(&wrp0, 0, 0);
assert(ch0 != NULL);
assert(intel_vvp_warp_check_easy_warp_capable(ch0) == 0);

// Configure channel
intel_vvp_warp_channel_config_t cfg;

// Configure in 4K, RGB Full colourspace
cfg.ram_addr = FRAMEBUF_BASE_ADDR;
cfg.cs = ERGB_FULL;
cfg.width_input = width;
cfg.height_input = height;
cfg.width_output = width;
cfg.height_output = height;
cfg.lfr = 0;

intel_vvp_warp_configure_channel(ch0, &cfg);	

// Mirror input video
// Enable video bypass, keep original resolution
intel_vvp_warp_bypass(ch0, 1, 0, width, height);
// Configure Easy warp mirror
intel_vvp_warp_set_easy_warp(ch0, 0x4);

// Rotate input video 90 degrees CCW
// Enable video bypass, flip input width and height
intel_vvp_warp_bypass(ch0, 1, 0, height, width);
// Configure Easy warp rotation
intel_vvp_warp_set_easy_warp(ch0, 0x01);	

// Release warp channel
assert(wrp0.num_engines > 0);

Warp latency parameters generation example

The example shows how to generate recommended minimum latency parameters for a given video transformation. These parameters are necessary to configure video pipeline for low latency operation.

// Example video and system clock
static constexpr uint32_t EXAMPLE_CLOCK	= 300000000;
// UHD video dimensions
static constexpr uint32_t WIDTH_UHD		= 3840;
static constexpr uint32_t HEIGHT_UHD		= 2160;
static constexpr uint32_t FULL_HEIGHT_UHD	= 2250;
// Output frame rate x100
static constexpr uint32_t OUTPUT_FRAME_RATE	= 6000;

// In this example system and video clock are the same
const uint32_t system_clock = EXAMPLE_CLOCK;
const uint32_t video_clock = EXAMPLE_CLOCK;

// Warp channel
intel_vvp_warp_channel_t* ch0{nullptr};

// Allocate and initialize a warp channel here
//	...

// Generate a 4K mesh for 5 degree CCW rotation
WarpConfigurator configurator{WarpDataHelper::GetHwContext(ch0)};

configurator.SetInputResolution(WIDTH_UHD, HEIGHT_UHD);
configurator.SetOutputResolution(WIDTH_UHD, HEIGHT_UHD);

WarpMeshSet mesh_set{configurator.GenerateMeshFromFixed()};

// Parameters required for warp data generation
WarpDataContext ctx{
WarpDataGenerator data_generator;

WarpDataPtr user_data = data_generator.GenerateData(ctx, mesh_set);

// Obtain latency params for the configured warp
WarpLatencyParams latency_params = data_generator.GenerateLatencyParams(ctx, user_data, system_clock, video_clock, FULL_HEIGHT_UHD, OUTPUT_FRAME_RATE);

// Upload and apply generated warp data here
// …
// intel_vvp_warp_apply_transform(ch0, …);
// …

// Pass on “output_latency” to the driver
intel_vvp_warp_set_output_latency(ch0, latency_params._output_latency);

// The “total_latency” member represents the recommended minimum offset
// between the input and output frames
// The value is in axi4s_vid_out_0_clock clock cycles
// Use the this parameter to configure the rest of the video pipeline
// as appropriate
//	latency_params._total_latency;
//assert(wrp0.num_engines > 0);