Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 12/31/2023
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. AXI-Stream Broadcaster Intel® FPGA IP x
10.1. About the AXI-Stream Broadcaster IP 10.2. AXI-Stream Broadcaster IP Parameters 10.3. AXI-Stream Broadcaster IP Interfaces
10.1. About the AXI-Stream Broadcaster IP x
10.1.1. AXI-Stream Broadcaster IP Features 10.1.2. AXI-Stream Broadcaster IP Performance and Resources
11. Bits per Color Sample Adapter Intel FPGA IP x
11.1. About the Bits per Color Sample Adapter IP 11.2. Bits per Color Sample Adapter IP Parameters 11.3. Bits per Color Sample Adapter IP Interfaces 11.4. Bits per Color Sample Adapter IP Registers 11.5. Bits per Color Sample Adapter Software API
11.1. About the Bits per Color Sample Adapter IP x
11.1.1. Bits per Color Sample Adapter IP Performance and Resources
12. Black Level Correction Intel® FPGA IP x
12.1. About the Black Level Correction IP 12.2. Black Level Correction IP Parameters 12.3. Black Level Correction IP Functional Description 12.4. Black Level Correction IP Registers 12.5. Black Level Correction IP Software API
12.1. About the Black Level Correction IP x
12.1.1. Black Level Correction IP Performance and Resources
12.3. Black Level Correction IP Functional Description x
12.3.1. Black Level Correction IP Interfaces
13. Black Level Statistics Intel® FPGA IP x
13.1. About the Black Level Statistics IP 13.2. Black Level Statistics IP Parameters 13.3. Black Level Statistics IP Interfaces 13.4. Black Level Statistics IP Registers 13.5. Black Level Statistics IP Software API
13.1. About the Black Level Statistics IP x
13.1.1. Black Level Statistics IP Performance and Resources
14. Chroma Key Intel® FPGA IP x
14.1. About the Chroma Key IP 14.2. Chroma Key IP Parameters 14.3. Chroma Key IP Interfaces 14.4. Chroma Key Replacement 14.5. Chroma Key IP Registers 14.6. Chroma Key IP Software API
14.1. About the Chroma Key IP x
14.1.1. Chroma Key IP Performance and Resources
15. Chroma Resampler Intel® FPGA IP x
15.1. About the Chroma Resampler IP 15.2. Chroma Resampler IP Parameters 15.3. Chroma Resampler IP Functional Description 15.4. Chroma Resampler IP Registers 15.5. Chroma Resampler IP Software API
15.1. About the Chroma Resampler IP x
15.1.1. Chroma Resampler Performance and Resources
15.3. Chroma Resampler IP Functional Description x
15.3.1. Chroma Resampler IP Interfaces
16. Clipper Intel® FPGA IP x
16.1. About the Clipper IP 16.2. Clipper IP Parameters 16.3. Clipper IP Interfaces 16.4. Clipper IP Registers 16.5. Clipper IP Software API
16.1. About the Clipper IP x
16.1.1. Clipper IP Performance and Resources
17. Clocked Video Input Intel® FPGA IP x
17.1. About the Clocked Video Input IP 17.2. Initializing the Clocked Video Input IP 17.3. Clocked Video Input IP Parameters 17.4. Clocked Video Input IP Interfaces 17.5. Clocked Video Input IP Registers 17.6. Clocked Video Input IP Software API
17.1. About the Clocked Video Input IP x
17.1.1. Clocked Video Input IP Features 17.1.2. Clocked Video Input IP Performance and Resources
18. Clocked Video to Full-Raster Converter Intel® FPGA IP x
18.1. About the Clocked Video to Full-Raster Converter IP 18.2. Clocked Video to Full-Raster Converter Parameters 18.3. Clocked Video to Full-Raster Converter Block Description 18.4. Clocked Video Converter to Full-Raster IP Registers
18.1. About the Clocked Video to Full-Raster Converter IP x
18.1.1. Clocked Video to Full-Raster Converter Features 18.1.2. Clocked Video to Full-Raster Converter Performance and Resources
18.3. Clocked Video to Full-Raster Converter Block Description x
18.3.1. Clocked Video to Full-Raster Converter Interfaces
19. Clocked Video Output Intel® FPGA IP x
19.1. About the Clocked Video Output IP 19.2. Clocked Video Output IP Parameters 19.3. Clocked Video Output IP Functional Description 19.4. Clocked Video Output IP Interfaces 19.5. Clocked Video Output IP Registers 19.6. Clocked Video Output IP Software API
19.1. About the Clocked Video Output IP x
19.1.1. Clocked Video Output IP Performance and Resources 19.1.2. Clocked Video Output IP Features
20. Color Space Converter Intel® FPGA IP x
20.1. About the Color Space Converter IP 20.2. Color Space Converter IP Parameters 20.3. Color Space Converter IP Functional Description 20.4. Color Space Converter IP Registers 20.5. Color Space Converter IP Software API
20.1. About the Color Space Converter IP x
20.1.1. Color Space Converter IP Features 20.1.2. Color Space Converter IP Performance and Resources
20.3. Color Space Converter IP Functional Description x
20.3.1. Color Space Converter IP Interfaces
21. Defective Pixel Correction Intel® FPGA IP x
21.1. About the Defective Pixel Correction IP 21.2. Defective Pixel Correction IP Parameters 21.3. Defective Pixel Correction IP Functional Description 21.4. Defective Pixel Correction IP Registers 21.5. Defective Pixel Correction IP Software API
21.1. About the Defective Pixel Correction IP x
21.1.1. Defective Pixel Correction IP Performance and Resources
21.3. Defective Pixel Correction IP Functional Description x
21.3.1. Defective Pixel Correction IP Interfaces
22. Deinterlacer Intel® FPGA IP x
22.1. About the Deinterlacer IP 22.2. Deinterlacer Parameters 22.3. Deinterlacer Interfaces 22.4. Deinterlacer IP Registers 22.5. Deinterlacer IP Software API
22.1. About the Deinterlacer IP x
22.1.1. Deinterlacer Performance and Resources
23. Demosaic Intel® FPGA IP x
23.1. About the Demosaic IP 23.2. Demosaic IP Parameters 23.3. Demosaic IP Functional Description 23.4. Demosaic IP Registers 23.5. Demosaic IP Software API
23.1. About the Demosaic IP x
23.1.1. Demosaic IP Performance and Resources
23.3. Demosaic IP Functional Description x
23.3.1. Demosaic IP Interfaces
24. FIR Filter Intel® FPGA IP x
24.1. About the FIR Filter 24.2. FIR Filter Parameters 24.3. FIR Filter IP Operation 24.4. FIR Filter Interfaces 24.5. FIR Filter Registers 24.6. FIR Filter IP Software API
24.1. About the FIR Filter x
24.1.1. FIR Filter IP Performance and Resources
24.3. FIR Filter IP Operation x
24.3.1. FIR Filter Processing 24.3.2. FIR Filter Precision 24.3.3. FIR Coefficient Specification 24.3.4. FIR Filter Symmetry 24.3.5. Result to Output Data Type Conversion
24.3.4. FIR Filter Symmetry x
24.3.4.1. No Symmetry 24.3.4.2. Horizontal Symmetry 24.3.4.3. Vertical Symmetry 24.3.4.4. Horizontal and Vertical Symmetry 24.3.4.5. Diagonal Symmetry
25. Frame Cleaner Intel® FPGA IP x
25.1. About the Frame Cleaner IP 25.2. Frame Cleaner IP Parameters 25.3. Frame Cleaner IP Functional Description 25.4. Frame Cleaner IP Interfaces 25.5. Frame Cleaner IP Registers 25.6. Frame Cleaner IP Software API
25.1. About the Frame Cleaner IP x
25.1.1. Frame Cleaner IP Performance and Resources
26. Full-Raster to Clocked Video Converter Intel® FPGA IP x
26.1. About the Full-Raster to Clocked Video Converter 26.2. Full Raster to Clocked Video Converter Parameters 26.3. Full-Raster to Clocked Video Converter Block Description 26.4. Full-Raster to Clocked Video Converter Registers
26.1. About the Full-Raster to Clocked Video Converter x
26.1.1. Full-Raster to Clocked Video Converter Features 26.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
26.3. Full-Raster to Clocked Video Converter Block Description x
26.3.1. Full Raster to Clocked Video Converter Interfaces
27. Full-Raster to Streaming Converter Intel® FPGA IP x
27.1. About the Full-Raster to Streaming Converter IP 27.2. Full-Raster to Streaming Converter Parameters 27.3. Full-Raster to Streaming Converter Block Description
27.1. About the Full-Raster to Streaming Converter IP x
27.1.1. Full-Raster to Streaming Converter Features 27.1.2. Full-Raster to Streaming Converter Performance and Resources
27.3. Full-Raster to Streaming Converter Block Description x
27.3.1. Full-Raster to Streaming Converter Interfaces
28. Genlock Controller Intel® FPGA IP x
28.1. About the Genlock Controller IP 28.2. Genlock Controller IP Parameters 28.3. Genlock Controller IP Functional Description 28.4. Using Genlock Controller IP Software 28.5. Genlock Controller IP Registers 28.6. Genlock Controller IP Software API
28.1. About the Genlock Controller IP x
28.1.1. Genlock Controller IP Performance and Resources
28.3. Genlock Controller IP Functional Description x
28.3.1. Genlock Controller IP Interfaces
28.4. Using Genlock Controller IP Software x
28.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 28.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 28.4.3. Setting the VCXO hold over 28.4.4. Restarting the Genlock Controller IP 28.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 28.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 28.4.7. Disturbing a Reference Clock (a cable pull)
29. Generic Crosspoint Intel® FPGA IP x
29.1. About the Generic Crosspoint IP 29.2. Generic Crosspoint IP Parameters 29.3. Generic Crosspoint IP Interfaces 29.4. Generic Crosspoint IP Registers 29.5. Generic Crosspoint IP Software API
29.1. About the Generic Crosspoint IP x
29.1.1. Generic Crosspoint IP Features 29.1.2. Generic Crosspoint Performance and Resources
30. Genlock Signal Router Intel® FPGA IP x
30.1. About the Genlock Signal Router IP 30.2. Genlock Signal Router IP Parameters 30.3. Genlock Signal Router IP Interfaces 30.4. Genlock Signal Router IP Registers 30.5. Genlock Signal Router IP Software API
30.1. About the Genlock Signal Router IP x
30.1.1. Genlock Signal Router IP Features 30.1.2. Genlock Signal Router IP Performance and Resources
31. Guard Bands Intel® FPGA IP x
31.1. About the Guard Bands IP 31.2. Guard Bands IP Parameters 31.3. Guard Bands IP Interfaces 31.4. Guard Bands IP Registers 31.5. Guard Bands IP Software API
31.1. About the Guard Bands IP x
31.1.1. Guard Bands IP Performance and Resources
32. Histogram Statistics Intel® FPGA IP x
32.1. About the Histogram Statistics IP 32.2. Histogram Statistics IP Parameters 32.3. Histogram Statistics IP Interfaces 32.4. Histogram Statistics IP Registers 32.5. Histogram Statistics IP Software API
32.1. About the Histogram Statistics IP x
32.1.1. Histogram Statistics IP Performance and Resources
33. Interlacer Intel® FPGA IP x
33.1. About the Interlacer IP 33.2. Interlacer IP Parameters 33.3. Interlacer IP Functional Description 33.4. Interlacer IP Registers 33.5. Interlacer IP Software API
33.1. About the Interlacer IP x
33.1.1. Interlacer IP Performance and Resources
33.3. Interlacer IP Functional Description x
33.3.1. Interlacer IP Interfaces
34. Mixer Intel® FPGA IP x
34.1. About the Mixer IP 34.2. Mixer IP Parameters 34.3. Mixer IP Functional Description 34.4. Mixer IP Registers 34.5. Mixer IP Software API
34.1. About the Mixer IP x
34.1.1. Mixer IP Performance and Resources
34.3. Mixer IP Functional Description x
34.3.1. Mixer IP Interfaces
35. Pixels in Parallel Converter Intel® FPGA IP x
35.1. About the Pixels in Parallel Converter IP 35.2. Pixels in Parallel Converter IP Parameters 35.3. Pixels in Parallel Converter Interfaces 35.4. Pixels in Parallel Converter Registers 35.5. Pixels in Parallel Converter IP Software API
35.1. About the Pixels in Parallel Converter IP x
35.1.1. Pixels in Parallel Converter IP Performance and Resources
36. Scaler Intel® FPGA IP x
36.1. About the Scaler 36.2. Scaler IP Parameters 36.3. Scaler IP Functional Description 36.4. Scaler IP Registers 36.5. Scaler IP Software API
36.1. About the Scaler x
36.1.1. Scaler IP Performance and Resources
36.2. Scaler IP Parameters x
36.2.1. Scaler Maximum Resolution
36.3. Scaler IP Functional Description x
36.3.1. Coefficient Selection 36.3.2. Coefficient Quantization 36.3.3. Filter Behavior at Edge Boundaries 36.3.4. Partial Frame Scaling 36.3.5. 422 and 420 Chroma Sampled Data Scaling 36.3.6. Scaler IP Interfaces
36.3.1. Coefficient Selection x
36.3.1.1. Updating Scaler IP Runtime Coefficients
37. Stream Cleaner Intel® FPGA IP x
37.1. About the Stream Cleaner IP 37.2. Stream Cleaner IP Parameters 37.3. Stream Cleaner IP Functional Description
37.1. About the Stream Cleaner IP x
37.1.1. Stream Cleaner IP Performance and Resources
37.3. Stream Cleaner IP Functional Description x
37.3.1. Stream Cleaner IP Interfaces
38. Switch Intel® FPGA IP x
38.1. About the Switch IP 38.2. Switch IP Parameters 38.3. Switch IP Functional Description 38.4. Switch IP Registers 38.5. Switch IP Software API
38.1. About the Switch IP x
38.1.1. Switch IP Performance and Resources
38.3. Switch IP Functional Description x
38.3.1. Switch IP Latency 38.3.2. Switch IP Interfaces
39. Tone Mapping Operator Intel® FPGA IP x
39.1. About the Tone Mapping Operator IP 39.2. TMO IP Parameters 39.3. TMO IP Block Description 39.4. TMO IP Registers 39.5. TMO IP Software API
39.1. About the Tone Mapping Operator IP x
39.1.1. TMO IP Features 39.1.2. TMO IP Performance and Resource Utilization
39.3. TMO IP Block Description x
39.3.1. TMO IP Interfaces 39.3.2. TMO IP Latency
40. Test Pattern Generator Intel® FPGA IP x
40.1. About the Test Pattern Generator IP 40.2. Test Pattern Generator IP Parameters 40.3. Test Pattern Generator IP Functional Description 40.4. Test Pattern Generator IP Registers 40.5. Test Pattern Generator IP Software API
40.1. About the Test Pattern Generator IP x
40.1.1. Test Pattern Generator IP Performance and Resources
40.3. Test Pattern Generator IP Functional Description x
40.3.1. Test Pattern Generator IP Interfaces
41. Unsharp Mask Intel® FPGA IP x
41.1. About the Unsharp Mask IP 41.2. Unsharp Mask IP Parameters 41.3. Unsharp Mask IP Functional Description 41.4. Unsharp Mask IP Registers 41.5. Unsharp Mask IP Software API
41.1. About the Unsharp Mask IP x
41.1.1. Unsharp Mask IP Performance and Resources
41.3. Unsharp Mask IP Functional Description x
41.3.1. Unsharp Mask IP Interfaces
42. Video and Vision Monitor Intel FPGA IP x
42.1. About the Video and Vision Monitor IP 42.2. Video and Vision Monitor IP Parameters 42.3. Video and Vision Monitor IP Functional Description 42.4. Video and Vision Monitor IP Registers 42.5. Video and Vision Monitor Software API
42.1. About the Video and Vision Monitor IP x
42.1.1. Video and Vision Monitor IP Performance and Resources
42.3. Video and Vision Monitor IP Functional Description x
42.3.1. Video and Vision Monitor IP Interfaces
43. Video Frame Buffer Intel® FPGA IP x
43.1. About the Video Frame Buffer IP 43.2. Video Frame Buffer IP Parameters 43.3. Video Frame Buffer IP Functional Description 43.4. Video Frame Buffer IP Registers 43.5. Video Frame Buffer IP Software API
43.1. About the Video Frame Buffer IP x
43.1.1. Video Frame Buffer Performance and Resources
43.3. Video Frame Buffer IP Functional Description x
43.3.1. Video Frame Buffer IP Interfaces
44. Video Frame Reader Intel FPGA IP x
44.1. About the Video Frame Reader IP 44.2. Video Frame Reader IP Parameters 44.3. Video Frame Reader IP Functional Description 44.4. Video Frame Reader IP Registers 44.5. Video Frame Reader IP Software API
44.1. About the Video Frame Reader IP x
44.1.1. Video Frame Reader IP Performance and Resources
44.3. Video Frame Reader IP Functional Description x
44.3.1. Video Frame Reader IP Interfaces
45. Video Frame Writer Intel FPGA IP x
45.1. About the Video Buffer Writer IP 45.2. Video Frame Writer IP Parameters 45.3. Video Frame Writer IP Functional Description 45.4. Video Frame Writer IP Registers 45.5. Video Frame Writer IP Software API
45.1. About the Video Buffer Writer IP x
45.1.1. Video Frame Writer IP Performance and Resources
45.3. Video Frame Writer IP Functional Description x
45.3.1. Video Frame Writer IP Interfaces
46. Video Streaming FIFO Intel® FPGA IP x
46.1. About the Video Streaming FIFO IP 46.2. Video Streaming FIFO IP Parameters 46.3. Video Streaming FIFO IP Interfaces
46.1. About the Video Streaming FIFO IP x
46.1.1. Video Streaming FIFO IP Performance and Resources
47. Video Timing Generator Intel® FPGA IP x
47.1. About the Video Timing Generator IP 47.2. Video Timing Generator IP Parameters 47.3. Video Timing Generator IP Functional Description 47.4. Video Timing Generator IP Interfaces 47.5. Video Timing Generator IP Registers 47.6. Video Timing Generator IP Software API
47.1. About the Video Timing Generator IP x
47.1.1. Video Timing Generator IP Features 47.1.2. Video Timing Generator IP Performance and Resources
48. Vignette Correction Intel® FPGA IP x
48.1. About the Vignette Correction IP 48.2. Vignette Correction IP Parameters 48.3. Vignette Correction IP Interfaces 48.4. Vignette Correction IP Registers 48.5. Vignette Correction IP Software API
48.1. About the Vignette Correction IP x
48.1.1. Vignette Correction IP Performance and Resources
49. Warp Intel® FPGA IP x
49.1. About the Warp IP 49.2. Warp IP Parameters 49.3. Warp IP Block Description 49.4. Warp IP Registers 49.5. Warp IP Software API
49.1. About the Warp IP x
49.1.1. Warp IP Features 49.1.2. Warp IP Performance and Resource Utilization
49.3. Warp IP Block Description x
49.3.1. Block Cache Tool 49.3.2. Warp IP Interfaces 49.3.3. Warp IP Latency 49.3.4. External Memory for Warp IP
49.5. Warp IP Software API x
49.5.1. Using Warp IP Software 49.5.2. Warp IP Software Code Examples
50. White Balance Correction Intel® FPGA IP x
50.1. About the White Balance Correction IP 50.2. White Balance Correction IP Parameters 50.3. White Balance Correction IP Functional Description 50.4. White Balance Correction IP Registers 50.5. White Balance Correction IP Software API
50.1. About the White Balance Correction IP x
50.1.1. White Balance Correction IP Performance and Resources
50.3. White Balance Correction IP Functional Description x
50.3.1. White Balance Correction IP Interfaces
51. White Balance Statistics Intel® FPGA IP x
51.1. About the White Balance Statistics IP 51.2. White Balance Statistics IP Parameters 51.3. White Balance Statistics IP Interfaces 51.4. White Balance Statistics IP Registers 51.5. White Balance Statistics IP Software API
51.1. About the White Balance Statistics IP x
51.1.1. White Balance Statistics IP Performance and Resources
52. Design Security x
52.1. Memory Subsystems 52.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. AXI-Stream Broadcaster Intel® FPGA IP
11. Bits per Color Sample Adapter Intel FPGA IP
12. Black Level Correction Intel® FPGA IP
13. Black Level Statistics Intel® FPGA IP
14. Chroma Key Intel® FPGA IP
15. Chroma Resampler Intel® FPGA IP
16. Clipper Intel® FPGA IP
17. Clocked Video Input Intel® FPGA IP
18. Clocked Video to Full-Raster Converter Intel® FPGA IP
19. Clocked Video Output Intel® FPGA IP
20. Color Space Converter Intel® FPGA IP
21. Defective Pixel Correction Intel® FPGA IP
22. Deinterlacer Intel® FPGA IP
23. Demosaic Intel® FPGA IP
24. FIR Filter Intel® FPGA IP
25. Frame Cleaner Intel® FPGA IP
26. Full-Raster to Clocked Video Converter Intel® FPGA IP
27. Full-Raster to Streaming Converter Intel® FPGA IP
28. Genlock Controller Intel® FPGA IP
29. Generic Crosspoint Intel® FPGA IP
30. Genlock Signal Router Intel® FPGA IP
31. Guard Bands Intel® FPGA IP
32. Histogram Statistics Intel® FPGA IP
33. Interlacer Intel® FPGA IP
34. Mixer Intel® FPGA IP
35. Pixels in Parallel Converter Intel® FPGA IP
36. Scaler Intel® FPGA IP
37. Stream Cleaner Intel® FPGA IP
38. Switch Intel® FPGA IP
39. Tone Mapping Operator Intel® FPGA IP
40. Test Pattern Generator Intel® FPGA IP
41. Unsharp Mask Intel® FPGA IP
42. Video and Vision Monitor Intel FPGA IP
43. Video Frame Buffer Intel® FPGA IP
44. Video Frame Reader Intel FPGA IP
45. Video Frame Writer Intel FPGA IP
46. Video Streaming FIFO Intel® FPGA IP
47. Video Timing Generator Intel® FPGA IP
48. Vignette Correction Intel® FPGA IP
49. Warp Intel® FPGA IP
50. White Balance Correction Intel® FPGA IP
51. White Balance Statistics Intel® FPGA IP
52. Design Security
53. Document Revision History for Video and Vision Processing Suite User Guide

36.4. Scaler IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 586.  Scaler IP RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_SCALER as appropriate and with an optional REG suffix
Address Register Access Description
Parameterization registers
0x0000 VID_PID RO

Read this register to retrieve scaler product ID.

This register always returns 0x6AF7_0234.

0x0004 VERSION RO

Read this register to retrieve the version information for the scaler.

0x0008 LITE_MODE RO Read this register to determine if Lite mode is on or off. This register returns 0 when you turn off Lite mode and 1 when you turn on Lite mode.
0x000C DEBUG_ENABLED RO Read this register to determine if Debug features is on or off. This register returns 1 if reads to other registers designated as RW return the last value the IP writes to the register, or an undefined value.
0x0010 PIXELS_IN_PARALLEL RO Read this register to determine the number of pixels processed per clock cycle.
0x0014 MAX_INPUT_WIDTH RO Read this register to determine the maximum supported input field width.
0x0018 MAX_OUTPUT_WIDTH RO Read this register to determine the maximum supported output field width.
0x001C ALGORITHM RO Read this register to determine which algorithm the scaler is configured to use. Returns 0 for Nearest neighbor, 1 for Bilinear and 2 for Polyphase.
0x0020 COEFFS_RUNTIME_LOAD RO Read this register to determine if updates to the coefficients at runtime via the Avalon memory-mapped agent interface are supported. Returns 1 if updates are supported and 0 otherwise.
0x0024 COEFF_MEM_INIT RO Read this register to determine if the scaler is configured with pre-initialized coefficients at reset. Returns 1 if the coefficients are preinitialized and 0 otherwise.
0x0028 V_SCALING_ENABLED RO Read this register to determine if the scaler is configured to support vertical scaling. Returns 1 if vertical scaling is supported and 0 otherwise.
0x002C V_NUM_TAPS RO Read this register to determine the number of vertical scaling filter taps.
0x0030 V_NUM_PHASES RO Read this register to determine the number of vertical scaling filter phases.
0x0034 V_NUM_BANKS RO Read this register to determine the number of vertical scaling filter coefficient banks.
0x0038 V_COEFFS_SIGNED RO Read this register to determine if the vertical scaling filter uses signed coefficients. Returns 1 is the coefficients are signed and 0 otherwise.
0x003C V_COEFFS_INT_BITS RO Read this register to determine the number of integer bits used to represent the vertical scaling filter coefficients.
0x0040 V_COEFFS_FRAC_BITS RO Read this register to determine the number of fraction bits that represent the vertical scaling filter coefficients.
0x0044 H_SCALING_ENABLED RO Read this register to determine if the scaler supports horizontal scaling. Returns 1 if horizontal scaling is supported and 0 otherwise.
0x0048 H_NUM_TAPS RO Read this register to determine the number of horizontal scaling filter taps.
0x004C H_NUM_PHASES RO Read this register to determine the number of horizontal scaling filter phases.
0x0050 H_NUM_BANKS RO Read this register to determine the number of horizontal scaling filter coefficient banks.
0x0054 H_COEFFS_SIGNED RO Read this register to determine if the horizontal scaling filter uses signed coefficients. Returns 1 is the coefficients are signed and 0 otherwise.
0x0058 H_COEFFS_INT_BITS RO Read this register to determine the number of integer bits to represent the horizontal scaling filter coefficients.
0x005C H_COEFFS_FRAC_BITS RO Read this register to determine the number of fraction bits to represent the horizontal scaling filter coefficients.
0x0060 to 0x0067 - - Reserved.
0x0068 V_PARTIAL_SCALING_ENABLED RO Read this register to determine if vertical partial scaling is on
0c006C H_PARTIAL_SCALING_ENABLED RO Read this register to determine if horizontal partial scaling is on
0x0070to 0x011F - - Unused.
Table 587.  Scaler IP Control and Debug RegistersFor more information, refer to Control Packets. In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_SCALER as appropriate and with an optional REG suffix
Address Register Access Description
Lite 101 Full
0x0120 IMG_INFO_WIDTH RW RO

When you turn on Lite mode, use this register to set the expected width of incoming video fields.

When you turn off Lite mode and turn on Debug features, this register returns the width that the scaler derives from information in the image information packet.

When you turn on Horizontal partial scaling, the value in this register specifies the number of pixels that this scaler receives in each incoming video line, including any overscan data.

0x0124 IMG_INFO_HEIGHT RW RO

When you turn on Lite mode, use this register to set the expected height of incoming video fields.

When you turn off Lite mode and turn on Debug features, this register returns the height that the scaler derives from information in the image information packet.

When you turn on Vertical partial scaling, the value in this register specifies the number of lines that this scaler receives in each incoming frame, including any overscan data.

0x0128 IMG_INFO_INTERLACE - RO When you turn off Lite mode and turn on Debug features, this register returns the interlace nibble that the scaler derives from information in the image information packet. Unused in lite mode.
0x012C Reserved - - Reserved
0x0130 IMG_INFO_COLORSPACE - RO When you turn off Lite mode and turn on Debug features, this register returns the color space that the scaler derives from information in the image information packet. Unused in lite mode.
0x0134 IMG_INFO_SUBSAMPLING - RO When you turn off Lite mode and turn on Debug features, this register returns the subsampling that the scaler derives from information in the image information packet. Unused in lite mode.
0x0138 IMG_INFO_COSITING - RO When you turn off Lite mode and turn on Debug features, this register returns the cositing that the scaler derives from information in the image information packet. Unused in lite mode.
0x013C IMG_INFO_FIELD_COUNT - RO When you turn off Lite mode and turn on Debug features, this register returns the field count that the scaler derives from information in the image information packet. Unused in lite mode.
0x012C to 0x013C - - - Unused.
0x0140 STATUS RO

Bit 0 : Status bit.

1 means scaler is processing a video field, 0 otherwise.

When you turn off Lite mode:

Bit 1 : Pending register updates bit.

Any writes to the settings register (0x0148 - 0x0154) cause the IP to raise pending register updates bit, to indicate outstanding changes to the scaling settings.

The IP lowers this bit at the next field boundary after a write to the COMMIT register.

0x0144 COMMIT RW Only use when you turn off Lite mode. The IP holds any changes to the scaling settings (not coefficients) via the register map until you issue a write to this register. The value you write is unimportant.
0x0148 OUTPUT_WIDTH RW

Write to this register to set the output field width. Unused if horizontal scaling is not enabled.

If you turn on Horizontal partial scaling, the value in this register specifies the number of output pixels that this scaler produces for each line.

0x014C OUTPUT_HEIGHT RW

Write to this register to set the output field height. Unused if vertical scaling is not enabled.

If you turn on Vertical partial scaling, the value in this register specifies the number of output lines that this scaler produces for each frame.

0x0150 H_BANK RW Write to this register to set the read bank for the horizontal scaling filter coefficients.
0x0154 V_BANK RW Write to this register to set the read bank for the vertical scaling filter coefficients
0x0158 TOTAL_IN_WIDTH RW Only if you turn on Horizontal partial image scaling. Write to this register to set the overall width of the tiled input frame.
0x015C TOTAL_OUT_WIDTH RW Only if you turn on Horizontal partial image scaling. Write to this register to set the overall width of the tiled output frame.
0x0160 H_POS_ERROR RW

Only if you turn on Horizontal partial image scaling. Write to this register to set the horizontal sub-pixel offset. If o s is the index of the first output pixel within the complete output frame that this scaler should produce, the horizontal sub-pixel offset is calculated as:

0x0164 H_PHASE_OFFSET RW

Only if you turn on Horizontal partial image scaling. Write to this register to set the horizontal phase offset. If o s is the index of the first output pixel within the complete output frame that this scaler should produce, the horizontal phase offset is calculated as:

0x0168 H_PHASE_ERROR RW

Only if you turn on Horizontal partial image scaling. Write to this register to set the horizontal sub-phase offset. If o s is the index of the first output pixel within the complete output frame that this scaler should produce, the horizontal sub-phase offset is calculated as:

0x016C H_EXTENDED_FILL RW Only if you turn on Horizontal partial image scaling. Write to this register to enable the left edge overscan feature. Write 1 to bit 0 to enable overscan, or 0 to bit 0 to disable overscan
0x0170 TOTAL_IN_HEIGHT RW Only if you turn on Vertical partial image scaling. Write to this register to set the overall height of the tiled input frame ().
0x0174 TOTAL_OUT_HEIGHT RW Only if you turn on Vertical partial image scaling. Write to this register to set the overall height of the tiled output frame ().
0x0178 V_POS_ERROR RW

Only if you turn on Vertical partial image scaling. Write to this register to set the vertical sub-pixel offset. If o s is the index of the first output line within the complete output frame that this scaler should produce, the vertical sub-pixel offset is calculated as:

0x017C V_PHASE_OFFSET RW

Only if you turn on Vertical partial image scaling. Write to this register to set the vertical phase offset. If o s is the index of the first output line within the complete output frame that this scaler should produce, the vertical phase offset is calculated as:

0x0180 V_PHASE_ERROR RW

Only if you turn on Vertical partial image scaling. Write to this register to set the vertical sub-phase offset. If o s is the index of the first output line within the complete output frame that this scaler should produce, then the vertical sub-phase offset is calculated as:

0x0184 V_EXTENDED_FILL RW Only if you turn on Vertical partial image scaling. Write to this register to enable the top edge overscan feature. Write 1 to bit 0 to enable overscan, or 0 to bit 0 to disable overscan
0x0188 to 0x01FC - - Unused.
0x0200 RT_COEFF_LOAD_BANK_SELECT WO Write to this register to set the index of the scaling filter coefficient bank that is being updated
0x0204 RT_COEFF_LOAD_PHASE_SELECT WO Write to this register to set the index of the scaling filter phase that you are updating
0x0208 RT_COEFF_LOAD_COMMIT WO Write 1 to this register to commit the coefficient information in the RT_COEFF_LOAD_TAP_X registers to the horizontal scaling filter coefficient bank and phase specified in RT_COEFF_LOAD_BANK_SELECT and RT_COEFF_LOAD_PHASE_SELECT respectively. Write 0 to this register to commit the coefficient information in the RT_COEFF_LOAD_TAP_X registers to the vertical scaling filter coefficient bank and phase specified in RT_COEFF_LOAD_BANK_SELECT and RT_COEFF_LOAD_PHASE_SELECT respectively.
0x020C-0x0308 RT_COEFF_LOAD_TAP_0 - RT_COEFF_LOAD_TAP_63 WO Up to 64 registers to set the new coefficient values for a vertical or horizontal scaling filter phase. If the vertical scaling filter has N taps, only the first N registers need to update before writing to the RT_COEFF_LOAD_COMMIT register. If the horizontal scaling filter has M taps, only the first M registers need to update before writing to the RT_COEFF_LOAD_COMMIT register.

Register Bit Descriptions

Table 588.  VID_PID
Name Bits Description
Scaler version ID and product ID 31:0 This register always returns 0x6AF7_0234.
  • 15:0 is the product ID and always returns 0x0234
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 589.  VERSION
Name Bits Description
Lite mode parameterization bit 7:0 Register map version. This returns 0x01.
QPDS patch revision 15:8 Returns 0x00 .
QPDS update revision 23:16 Updated for each release. For 214, returns 0x04 .
QPDS major revision 31:24 Updated for each release. For 21.4, returns 0x15.
Table 590.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 31:0 Returns 1 if Lite mode is on and 0 otherwise.
Table 591.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 31:0 Returns 1 if Debug features is on and 0 otherwise.
Table 592.  PIXELS_IN_PARALLEL
Name Bits Description
Pixels in parallel 31:0 Number of pixels processed per clock cycle.
Table 593.  MAX_INPUT_WIDTH
Name Bits Description
Maximum input width 31:0 Maximum supported input field width.
Table 594.  MAX_OUTPUT_WIDTH
Name Bits Description
Maximum output width 31:0 Maximum supported output field width.
Table 595.  ALGORITHM
Name Bits Description
Algorithm 31:0 Returns 0 for Nearest neighbor, 1 for Bilinear and 2 for Polyphase.
Table 596.   COEFFS_RUNTIME_LOAD
Name Bits Description
Runtime load 31:0 Returns 1 if Runtime coefficient updates is on and 0 otherwise. Only valid for Polyphase.
Table 597.   COEFF_MEM_INIT
Name Bits Description
Coefficient memory initialized 31:0 Returns 1 if the scaling filter coefficient memory is preinitialized at reset and 0 otherwise. Only valid for Polyphase.
Table 598.   V_SCALING_ENABLED
Name Bits Description
Vertical scaling enabled 31:0 Returns 1 if Enable vertical scaling is on and 0 otherwise
Table 599.   V_NUM_TAPS
Name Bits Description
Vertical scaling filter taps 31:0 Returns the number of vertical scaling filter taps.
Table 600.   V_NUM_PHASES
Name Bits Description
Vertical scaling filter phases 31:0 Returns the number of vertical scaling filter phases. Only valid for Polyphase.
Table 601.   V_NUM_BANKS
Name Bits Description
Vertical scaling filter coefficient banks 31:0 Returns the number of vertical scaling filter coefficient banks. Only valid if polyphase scaling is selected.
Table 602.   V_COEFFS_SIGNED
Name Bits Description
Vertical scaling filter coefficients signed 31:0 Returns 1 if the vertical scaling filter coefficients are signed values and 0 otherwise. Only valid for Polyphase.
Table 603.   V_COEFFS_INT_BITS
Name Bits Description
Vertical scaling filter coefficients integer bits 31:0 Returns the number of integer bits used to represent the vertical scaling filter coefficients. Only valid for Polyphase.
Table 604.   V_COEFFS_FRAC_BITS
Name Bits Description
Vertical scaling filter coefficients fraction bits 31:0 Returns the number of fraction bits to represent the vertical scaling filter coefficients. Only valid for Polyphase.
Table 605.   H_SCALING_ENABLED
Name Bits Description
Horizontal scaling enabled 31:0 Returns 1 if horizontal scaling is enabled and 0 otherwise.
Table 606.  H_NUM_TAPS
Name Bits Description
Horizontal scaling filter taps 31:0 Returns the number of horizontal scaling filter taps.
Table 607.   H_NUM_PHASES
Name Bits Description
Horizontal scaling filter phases 31:0 Returns the number of horizontal scaling filter phases. Only valid for Polyphase.
Table 608.   H_NUM_BANKS
Name Bits Description
Horizontal scaling filter coefficient banks 31:0 Returns the number of horizontal scaling filter coefficient banks. Only valid for Polyphase.
Table 609.   H_COEFFS_SIGNED
Name Bits Description
Horizontal scaling filter coefficients signed 31:0 Returns 1 if the horizontal scaling filter coefficients are signed values and 0 otherwise. Only valid for Polyphase.
Table 610.   H_COEFFS_INT_BITS
Name Bits Description
Horizontal scaling filter coefficients integer bits 31:0 Returns the number of integer bits to represent the horizontal scaling filter coefficients. Only valid for Polyphase.
Table 611.   H_COEFFS_FRAC_BITS
Name Bits Description
Horizontal scaling filter coefficients fraction bits 31:0 Returns the number of fraction bits to represent the horizontal scaling filter coefficients. Only valid for Polyphase.
Table 612.  V_PARTIAL_SCALING_ENABLED
Name Bits Description
Vertical partial image scaling enabled 31:0 Returns 1 if you turn on vertical partial image scaling and 0 otherwise
Table 613.   H_PARTIAL_SCALING_ENABLED
Name Bits Description
Horizontal partial image scaling enabled 31:0 Returns 1 if you turn on horizontal partial image scaling and 0 otherwise
Table 614.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

When Lite mode is on, write to this register to set the expected width of the incoming video fields.

For full parameterizations with debug features enabled, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 615.   IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

When Lite mode is on, write to this register to set the expected height of the incoming video fields.

For full parameterizations with debug features enabled, this register reads the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 616.  IMG_INFO_INTERLACE
Name Bits Description
IntlaceNibble bits 3:0

When Lite mode is on, this register has no function.

When Lite mode is off with Debug features on, this register returns the intlaceNibble field from the most recently received image information packet .

unused 31:4 Unused.
Table 617.  IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0

When Lite mode is on, this register has no function.

When Lite mode is off with Debug features on, this register returns the 7 bit CSP field from the most recently received image information packet.

unused 31:7 Unused.
Table 618.  IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0

When Lite mode is on, this register has no function.

When Lite mode is off with Debug features on, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 619.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

When Lite mode is on, this register has no function.

When Lite mode is off with Debug features on,, this register returns the COSITE field from the most recently received image information packet.

unused 31:2 Unused.
Table 620.  IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0

When Lite mode is on, this register has no function.

When Lite mode is off with Debug features on,, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.

unused 31:7 Unused.
Table 621.  STATUS
Name Bits Description
Status bit 0 1 means scaler is processing a video field, 0 otherwise.
Pending register updates bit 1 1 means scaler has pending updates, 0 otherwise
unused 31:2 Unused.
Table 622.  COMMIT
Name Bits Description
unused 31:0 Unused.
Table 623.  OUTPUT_WIDTH
Name Bits Description
Output width 15:0 Output field width
unused 31:16 Unused.
Table 624.  OUTPUT_HEIGHT
Name Bits Description
Output height 15:0 Output field height
unused 31:16 Unused.
Table 625.  H_BANK
Name Bits Description
Horizontal scaling filter coefficient read bank 3:0 Horizontal scaling filter coefficient read bank.
unused 31:4 Unused.
Table 626.  V_BANK
Name Bits Description
Vertical scaling filter coefficient read bank 3:0 Vertical scaling filter coefficient read bank.
unused 31:4 Unused.
Table 627.  TOTAL_IN_WIDTH
Name Bits Description
Total input frame width 15:0 Width of the complete, tiled input frame (only used if Horizontal partial image scaling is turned on)
Unused 31:4 Unused.
Table 628.  TOTAL_OUT_WIDTH
Name Bits Description
Total output frame width 15:0 Width of the complete, tiled output frame (only used if Horizontal partial image scaling is turned on)
Unused 31:4 Unused.
Table 629.  H_POS_ERROR
Name Bits Description
Horizontal sub-pixel offset 15:0 Horizontal subpixel offset (only used if Horizontal partial image scaling is turned on)
Unused 31:4 Unused.
Table 630.  H_PHASE_OFFSET
Name Bits Description
Horizontal phase offset 15:0 Horizontal phase offset (only used if Horizontal partial image scaling is turned on)
Unused 31:4 Unused.
Table 631.  H_PHASE_ERROR
Name Bits Description
Horizontal sub-phase offset 15:0 Horizontal subphase offset (only used if Horizontal partial image scaling is turned on)
Unused 31:4 Unused.
Table 632.  H_EXTENDED_FILL
Name Bits Description
Enable horizontal left edge overscan 0 Enable horizontal left edge overscan (only used if Horizontal partial image scaling is turned on)
Unused 31:1 Unused.
Table 633.  TOTAL_IN_HEIGHT
Name Bits Description
Total input frame height 15:0 Height of the complete, tiled input frame (only used if Vertical partial image scaling is turned on)
Unused 31:4 Unused.
Table 634.  TOTAL_OUT_HEIGHT
Name Bits Description
Total output frame height 15:0 Height of the complete, tiled output frame (only used if Vertical partial image scaling is turned on)
Unused 31:16 Unused.
Table 635.  V_POS_ERROR
Name Bits Description
Vertical sub-pixel offset 15:0 Vertical subpixel offset (only used if Vertical partial image scaling is turned on)
Unused 31:16 Unused.
Table 636.  V_PHASE_OFFSET
Name Bits Description
Vertical phase offset 15:0 Vertical phase offset (only used if Vertical partial image scaling is turned on)
Unused 31:16 Unused.
Table 637.  V_PHASE_ERROR
Name Bits Description
Vertical sub-phase offset 15:0 Vertical subphase offset (only used if Vertical partial image scaling is turned on)
Unused 31:16 Unused.
Table 638.  V_EXTENDED_FILL
Name Bits Description
Enable vertical top edge overscan 0 Enable vertical top edge overscan (only used if Vertical partial image scaling is turned on)
Unused 31:1 Unused.
Table 639.  RT_COEFF_LOAD_BANK_SELECT
Name Bits Description
Coefficient write bank 3:0 Index of coefficient bank to be updated
unused 31:4 Unused.
Table 640.  RT_COEFF_LOAD_PHASE_SELECT
Name Bits Description
Coefficient write phase 7:0 Index of coefficient phase to be updated
unused 31:8 Unused.
Table 641.  RT_COEFF_LOAD_COMMIT
Name Bits Description
unused 31:0 Unused.
Table 642.  RT_COEFF_LOAD_TAP_X
Name Bits Description
Coefficient value coeff_width-1:0 Coefficient value for filter tap X
unused 31:coeff_width Unused.
101

When you turn on lite mode, registers are RW only if you turn on Debug features, otherwise they are WO. For full, turn off lite mode.

Level Two Title