Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

20.3. Color Space Converter IP Functional Description

The inputs and outputs of the IP support 8 to 16 bits per pixel per color plane.

Input and Output Data Types

If the conversion requires you to specify minimum or maximum values, which the input or output cannot lie outside of, use the Guard Bands Intel FPGA IP. The Guard Bands Intel FPGA IP can be instantiated before, after, or before and after, depending on the requirements of the design. You can use the Guard Bands Intel FPGA IP if you use the Color Space Converter in a pipeline with signed data.

Color Space Conversion

You convert between color spaces by providing an array of nine coefficients and three summands that relate color spaces.

You can set these coefficients and summands at compile time, or you can enable the Avalon memory-mapped interface to change them dynamically at run-time.

Given a set of nine coefficients [A0, A1, A2, B0, B1, B2, C0, C1, C2] and a set of three summands [S0, S1, S2], the Color Space Converter calculates the output values for color planes 0, 1, and 2 (denoted dout_0, dout_1, and dout_2):

  • dout_0 = (A0 × din_0) + (B0 × din_1) + (C0 × din_2) + S0
  • dout_1 = (A1 × din_0) + (B1 × din_1) + (C1 × din_2) + S1
  • dout_2 = (A2 × din_0) + (B2 × din_1) + (C2 × din_2) + S2

din_0, din_1, and din_2 are inputs read from color planes 0, 1, and 2.

The Color Space Converter Intel FPGA IP supports the following predefined conversions that are available through the Platform Designer presets:

  • Computer B’G’R’ to CbY’Cr: SDTV
  • CbY’Cr: SDTV to Computer B’G’R’
  • Computer B’G’R’ to CbY’Cr: HDTV
  • CbY’Cr: HDTV to Computer B’G’R’
  • Studio B’G’R’ to CbY’Cr: SDTV
  • CbY’Cr: SDTV to Studio B’G’R’
  • Studio B’G’R’ to CbY’Cr: HDTV
  • CbY’Cr: HDTV to Studio B’G’R’

The IP assigns the values in the order indicated by the conversion name. For example, if you select Computer B’G’R’ to CbY’Cr: SDTV, din_0 = B’, din_1 = G’, din_2 = R’, dout_0 = Cb, dout_1 = Y’, and dout_2 = Cr. As the Intel FPGA Streaming Video Protocol states, din_0 occupies the LSBs of the word, din_1 the middle bits, and din_2 the MSBs. For example, for 8 bits per sample and one of the predefined conversions inputs B’G’R’, din_0 carries B’ in bits 0–7, din_1 carries G’ in bits 8–15, and din_2 carries R’ in bits 16–23.

Predefined Conversions

When using a predefined conversion, the precision of the coefficients and summands must still be defined. The predefined coefficients also only are available if you turn off Memory-Mapped control. Otherwise, the coefficients must be set at runtime using the Avalon memory-mapped interface.

Predefined conversions are only defined for input and output bits per pixel per color plane equal to 8, 10, and 12. You must manually scale the summands accordingly when using different bits per color plane values. If you use different input and output bits per pixel per color plane, you must also shift the results by the correct number of binary places to compensate. For example, to convert from 10-bit CbYCr' to 8-bit Computer B'G'R', select the conversion preset for 10-bit CbYCr' to 10-bit computer B'G'R'. The summands are already scaled for a 10-bit input, so they remain unchanged. Change the output bits per color plane value from 10 to 8 on the parameter editor and follow the instructions of the warning message to shift the results by the correct number of binary places (2 places to the left).

Always check the matrix of coefficients after applying a predefined conversion or after custom modifications. If the differences between the desired floating-point coefficient values and their actual fixed-point quantized values indicate an unacceptable loss of precision, you must increase the number of integer and or fractional bits to fix the problem.

Output Data Type Conversion

After the calculation, the fixed-point type of the results the IP must convert to the integer data type of the output.

The IP performs this conversion in four stages, in the following order:

  1. Scales result. You can choose to scale up the results, increasing their range, which is useful to quickly increase the color depth of the output. The available options are a shift of the binary point right –16 to +16 places. The IP implements the scale as a simple shift operation so it does not require multipliers
  2. Removes fractional bits. If any fractional bits exist, you can choose to remove them:
    • Truncate to integer. Fractional bits are removed from the data. This is equivalent to rounding towards negative infinity.
    • Round-half up. Round up to the nearest integer. If the fractional bits equal 0.5, rounding is towards positive infinity.
    • Round-half even. Round to the nearest integer. If the fractional bits equal 0.5, rounding is towards the nearest even integer.
  3. Converts from signed to unsigned. If any negative numbers can exist in the results and the output type is unsigned, they are saturated to the minimum output value.
  4. Constrain to range. Logic that saturates the results to the minimum and maximum output values:
    • If any of the results are not within the minimum and maximum values allowed by the output bits per pixel, the values are automatically constrained to this range.
    • If greater control is required over the lower and upper values, consider instantiating a Guard Bands Intel FPGA IP after the Color Space Converter