Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide
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22.4. Deinterlacer IP Registers

Each register is either read-only (RO) or read-write (RW).

Register Bit Descriptions

In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_DEINTERLACER as appropriate and with an optional REG suffix.

Table 328.  Control Registers
Address Register Access Description
Lite 60 Full
Parameterization registers
0x0000 PROD_ID RO RO Read this register for the Deinterlacer product ID. This register always returns 0x6AF7_023A.
0x0004 VER RO RO Read this register for the version information for the Deinterlacer.
0x0008 LITE_MODE RO RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when Lite mode is off and 1 when on.

0x000C DEBUG_ENABLED RO RO Read this register to determine if Debug features is on.
0x0010 MAX_WIDTH RO RO Read this register to determine the maximum supported frame width (bob deinterlacer only).
0x0014 DIL_MODE RO RO Read this register to determine the deinterlacing algorithm. Returns 0 for the bob algorithm. Returns 1 for the weave algorithm.
0x0018 BOB_DIL_MODE RO RO Read this register to determine the Bob deinterlacing mode. Returns 0 if deinterlacing F0 fields only, returns 1 if deinterlacing F1 fields only, otherwise returns 2. The content of this register is undefined if you select Weave for Deinterlacing mode.
0x001C MEM_BASE_ADDR RO RO Read this register for the base address of stored field in memory. 61
0x0020 MEM_LINE_STRIDE RO RO Read this register for the line stride in memory. 61
0x0024 BPS RO RO

Read this register for the number of bits per symbol configured. 61

0x0028 NUMBER_OF_COLOR_PLANES RO RO Read this register for the number of color planes. 61
0x002C PIXELS_IN_PARALLEL RO RO Read this register for the number of pixels in parallel. 61
0x0030 PACKING RO RO Read this register for the pixel packing scheme.61
0x0034 to 0x011F - - - Unused.
Control and debug registers

For more information, refer to Control Packets

0x0120 IMG_INFO_WIDTH RW RO For lite designs, the expected width of the incoming video fields. For full, the received width in the IP derives from the image information packets.
0x0124 IMG_INFO_HEIGHT RW RO For lite designs, the expected height of the incoming video fields. For full the received height in the IP derives from the image information packets.
0x0128 IMG_INFO_INTERLACE RW RO For lite designs, the expected interlace information of the incoming video fields. For full, the received interlace information in image information packets.
0x012C RESERVED RW RO Unused.
0x0130 IMG_INFO_COLORSPACE RW RO For lite designs, the expected color space of the incoming video fields. For full, the received color space in image information packets.
0x0134 IMG_INFO_SUBSAMPLING RW RO For lite designs, the expected chroma subsampling of the incoming video fields. For full, the received chroma subsampling in image information packets.
0x0138 IMG_INFO_COSITING RW RO For lite designs, the expected chroma co-siting of the incoming video fields. For full, the received chroma co-siting in image information packets.
0x013C IMG_INFO_FIELD_COUNT - RO The received field count field in image information packets.
0x0140 INPUT_STATUS RO RO

Bit 0: input status bit.

1 = Deinterlacer is receiving and processing a video field, 0 otherwise.

Table 329.  PROD_ID
Name Bits Description
Deinterlacer product ID 31:0 This register always returns 0x6AF7_023A.
Table 330.  VER
Name Bits Description
Register map version 7:0 Register map version.
Unused 15:8 Unused. Returns 0x00
QPDS minor revision 23:16 Updated for each release. For 21.4, returns 0x04
QPDS major revision 31:24 Updated for each release. For 21.4, returns 0x15.
Table 331.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on lite mode.
Unused 31:1 Unused.
Table 332.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 333.  DIL_MODE
Name Bits Description
Deinterlacer mode 31:0 Returns 0 if the IP is using a bob algorithm. Returns 1 if the IP is using a weave algorithm.
Table 334.  MAX_WIDTH Bob deinterlacer only
Name Bits Description
Max width 31:0 This register returns the maximum supported frame width.
Table 335.  BOB_DIL_MODEBob deinterlacer only
Name Bits Description
Bob deinterlacer mode 31:0 Returns the bob deinterlacing mode. Returns 1 if deinterlacing F0 fields only, returns 2 if deinterlacing F1 fields only, otherwise returns 3.
Table 336.  MEM_BASE_ADDRWeave deinterlacer only
Name Bits Description
Membase address 31:0 Returns the base address of stored field in memory.
Table 337.  MEM_LINE_STRIDEBob deinterlacer only
Name Bits Description
Memline stride 31:0 Returns the line stride in memory.
Table 338.  PACKING
Name Bits Description
Packing 31:0

Returns the packing scheme:

  • 0= Perfect packing
  • 1= Color packing
  • 2= Pixel packing
Table 339.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

When you turn on lite mode, write to this register to set the expected width of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the width-1field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 340.   IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

When you turn on lite mode, write to this register to set the expected height of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 341.  IMG_INFO_INTERLACE
Name Bits Description
InterlaceNibble bits 3:0
When you turn on lite mode, write to this register to set the expected interlacing of the incoming video fields:
  • Set bit 3 of this register high to indicate interlaced video
  • Set bit 3 low to indicate progressive video.
  • The IP does not use bits [2:0].

When you turn off lite mode and turn on Debug features, this register returns the

intlaceNibblefield from the most recently received image information packet.

unused 31:4 Unused.
Table 342.  IMG_INFO_COLORSPACE
Name Bits Description
CSPcode bits 6:0

When you turn on lite mode, write to this register to set the expected color space of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the 7 bit CSP field from the most recently received image information packet.

unused 31:7 Unused.
Table 343.  IMG_INFO_SUBSAMPLING
Name Bits Description
CSPSubSa code bits 1:0

When you turn on lite mode, write to this register to set the expected chroma subsampling of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 344.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

When you turn on lite mode, write to this register to set the expected chroma co-siting of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the COSITE field from the most recently received image information packet.

unused 31:2 Unused.
Table 345.  IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0

When you turn on lite mode, this register has no function.

When you turn off lite mode and turn on Debug features, this register returns the 7 bit

FIELD_COUNTfield from the most recently received image information packet.

unused 31:7 Unused.
Table 346.   INPUT_STATUS
Name Bits Description
Status bit 0 1= Deinterlacer is receiving and processing a video field, 0 otherwise.
60

When you turn on lite mode, registers are RW only if you turn on Debug features, otherwise they are WO. For full, turn off lite mode.

61 The content of this register is undefined if you select Bob for Deinterlacing mode.