Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

36.3.3. Filter Behavior at Edge Boundaries

For the Scaler IP, when you select Polyphase and select N filter taps, (N-1)/2 of these taps are above (vertical scaling) or to the left of (horizontal scaling) the center tap of the filter. N/2 of the taps are below (vertical scaling) or to the right of (horizontal scaling) the center pixel.

When scaling pixels around the top, bottom, left or right edges (boundaries) of the image, the filter taps above, below, to the left of or to the right of the center pixel naturally attempt to sample pixels that do not exist as they are in off-screen locations. To avoid using undefined data in these taps, the scaler detects when any tap is off-screen and replaces the data in that tap with data from an on-screen pixel. The Edge behavior parameter allows you to choose between two methods for filling the off-screen taps:

  • Replicate edge pixels. The IP replicates the pixel closest to the edge to fill all off-screen taps
  • Mirror edge pixels. The pixels leading up to the image edge reflect into the off-screen area, just as if a mirror is at the edge of the image. The reflected pixel values fill any off-screen taps.

Edge mirroring for a filter with N taps requires a minimum input image size of N/2 pixels to successfully fill all off-screen taps. Input images smaller than this minimum create undefined outputs. Edge replication works for all image sizes, down to 1x1 pixel. You cannot swap between edge methods at runtime.

You can only select this parameter if you select Polyphase scaling. Nearest neighbor scaling has no filter and no off-screen taps. Bilinear scaling requires a 2 tap filter, but edge replication and edge mirroring give the same result when the number of taps is 2, so the parameter is not required.