Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

17.2. Initializing the Clocked Video Input IP

The IP provides an Avalon memory-mapped interface, which you can use as a control interface to configure the IP. Initially, the IP is disabled and does not transmit any data or video. However, the Clocked Video Input IP still detects the format of the clocked video input and accepts data on the input video interface.

To start the output of the IP:

  1. Write a 1 to control register bit 0 to enable the clocked video input block
  2. Write a 1 to control register bit 4 to enable Vsync and Hsync autopolarity detection.
  3. Optionally, write a 1 to control register bit 3 to enable the frame cleaner logic.
  4. Optionally, write the minimum expected number of frames for F0 and F1 to control register bits 23:16 to enable autodetect interlaced video format mode. If you write zeros to this set of bits, the IP does not automatically auto-detect video interlaced formats.
  5. Write the expected output video height and width values to ref_lock_cfg1 register. The IP only starts transmitting video on the output interface when the values on ref_lock_cfg1 matches the values on registers active_line_count and total_line_count.
  6. Write the expected number of frames and output video lines values to ref_lock_cfg2 register. The IP only starts transmitting video on the output interface when the values on ref_lock_cfg2 are matched.
  7. Alternatively, if you write zeros to ref_lock_cfg1 and ref_lock_cfg2, the IP does not try to match any specific output video resolution values and immediately produces video.
  8. Optionally, set the values for each of the color planes that the frame cleaner use to do the padding on the output video frame in case a cable is pulled.
  9. Read status register bit 4. When this bit is 1, the IP starts transmitting video. The transmission starts on the next start of frame boundary.