Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide Updating Scaler IP Runtime Coefficients

If you select polyphase and turn on runtime coefficient updates, you can edit the values in the horizontal and vertical scaling coefficient memories at any time via the Avalon memory-mapped agent interface.

To minimize the implementation cost of the coefficient memories, you cannot directly access the value of each coefficient through a single read or write to the register map. You must write the values for the coefficients in a given phase (vertical or horizontal) to a set of addresses in the register map. Then declare through separate addresses which phase and which bank the IP writes the coefficients to.

  1. Write the values of the coefficients for one phase to the RT_COEFF_LOAD_TAP_Xregisters (0 <= X < 64, addresses 0x020C to 0x0308). The IP has 64 addresses into which you may write new coefficients. If the coefficient phase you are updating only has coefficients for N taps (where N < 64), you need only write values to the first N addresses in this range.
  2. Write the index of the bank to which the IP should write this phase of coefficients to the RT_COEFF_LOAD_BANK_SELECT register (address 0x0200).
  3. Write the index of the phase to which the IP should write the coefficients to the RT_COEFF_LOAD_PHASE_SELECT register (address 0x0204).
  4. Write to the RT_COEFF_LOAD_COMMIT register (address 0x208) to commit the new coefficients to the specified phase in the specified bank. Write 1 to this register if it is a horizontal scaling filter coefficient phase, and 0 if it is a vertical scaling filter coefficient phase.

You must repeat this process for every phase in every bank that you want to update. Unlike updates to settings registers (such as the output field width), coefficient updates take immediate effect. The IP does not hold them until a frame boundary. To avoid the IP updating coefficients in the middle of a frame, Intel recommends using at least two banks of coefficients. This way the software controlling the system can make updates to the coefficients in one bank, while the scaler reads coefficients for processing from the other bank. When the coefficient updates are complete, the software can swap the coefficient read bank to the newly updated bank by updating the value in the H_BANK or V_BANK address in the register map. These registers are standard settings registers, so the update to the coefficient read bank only takes effect at a frame boundary.