Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

41.3. Unsharp Mask IP Functional Description

The IP creates an unsharp mask by first calculating an approximation to the input image luminance using the input luminance equation:

Equation 9. Input Luminance

The IP then performs a low-pass Gaussian blur (low-pass filter) of .

The IP subtracts this filtered luminance from the original luminance to get the high-frequency components of the luminance.

The IP multiplies this value by the strength to obtain the sharpened luminance. The following equation shows this process.

Equation 10. Sharpened LuminanceThe equation shows that a strength of 0 gives Luma OUT equal to Luma IN .

The IP creates the final output image by calculating a ratio of , which scales the RGB components of the original image. A strength of 0 results in unity ratio.

Equation 11. Final Output Image RGB Scaling

The unsharp mask has an Avalon® memory-mapped agent interface to allow run-time control of the strength of the unsharp mask operation. Set the strength to zero for the IP to pass through the video unchanged.

You need not start the IP via the run-time interface as it starts processing video on its input as soon as it comes out of reset

Changes to the strength run-time control register take effect on the next video line.

Register Behavior

Write values to the control and debugging registers to set video field dimensions. Turn on Debug Features in the GUI so you can read back these values.


The IP latency under ideal conditions is three video lines plus an additional 34 clock cycles. This latency increases if the streaming video output experiences backpressure via its axi4s_vid_out_tready input. Backpressure increases the latency by the same amount of cycles.

The sharpening strength register setting does not change the latency.