Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

35.1. About the Pixels in Parallel Converter IP

The Intel FPGA streaming video protocol allows multiple pixels to be transmitted in a single clock cycle (beat). The number of pixels the interface transmits per beat (pixels in parallel) is a fixed property of the interface. The IP converts from one value of pixels in parallel at the input interface to a higher or lower number of pixels in parallel at the output interface. The IP supports any number of pixels in parallel between 1 and 8 for both the input and output interface and supports all possible conversions.

To help manage data rates, the IP includes the option for a FIFO buffer on the datapath. For conversions that lower the pixels in parallel, the IP locates the FIFO buffer at the input interface, before the conversion logic. For conversions that increase the pixels in parallel, the IP locates the FIFO buffer at the output interface, after the conversion logic. A parameter selects either single clock or dual clock mode for the FIFO buffer. If you select dual clock mode, the input and output interfaces can run on different clock domains.

To correctly implement the pixels in parallel conversion in all cases, the IP must know how many pixels are in each video line. Without this information the IP does not know how many of the pixels in parallel are valid on the final beat of each video line packet. If you configure the IP for use with the full variant of the Intel FPGA streaming video protocol, you can obtain this information directly from the image information packets contained within the video stream. The IP has no requirement for a register map or for the control agent interface to access it. If you configure for the lite variant of the protocol, the video stream has no image information so you must supply the line length through the register map, via the control agent interface. Selecting to use the lite variant of the protocol automatically enables the control agent interface.