Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

22.1. About the Deinterlacer IP

The IP takes a stream of interlaced video fields and outputs progressive frames generated using a bob or weave algorithm. The IP passes progressive video frames through unchanged.

The bob algorithm produces output frames by filling in the missing lines from the current field with the linear interpolation of the lines above and below.. The deinterlacing algorithm can be setup for:

  • Deinterlacing F0 fields while dropping F1 fields
  • Deinterlacing F1 fields while dropping F0 fields
  • Deinterlacing both F0 and F1 fields

For the bob deinterlacer, with a regular input sequence of alternating field types, the frame rate on the output matches the input field rate when deinterlacing both F0 and F1 fields. Otherwise the IP halves the field rate.

The weave algorithm creates an output frame by filling all the missing lines in the current field with lines from the previous field. With a regular input sequence of alternating field types, the IP halves the field rate. The weave deinterlacer includes an optional FIFO buffer with fixed depth 1024.

The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. For full variants, the deinterlacer IP decodes input resolutions and field type by reading image information packets. Lite variants use the register interface to determine input resolutions and whether the video is progressive or interlaced. Lite variants then decode the axi4s_vid_in_tuser[1] signal to determine the incoming field's interlaced type. If you require weave or motion adaptive deinterlacing, use protocol converters and the video and image processing suite deinterlacer II IP.