Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

25.5. Frame Cleaner IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 396.  Frame Cleaner IP Control Registers

In the software API these register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_CLEANER as appropriate and with an optional REG suffix

Address Register Access Description
Parameterization Registers
0x0000 PROD_ID RO

Read this register to retrieve the frame cleaner product ID.

This register always returns 0x6AF7_023E.

0x0004 VER RO

Read this register to retrieve the version information for the Intel Quartus release that Intel used to build the frame cleaner.

0x0008 LITE_MODE RO

Read this register to determine if lite mode is on.

This register returns 1 if lite mode is on and 0 if lite mode is off

0x000C DEBUG_ENABLED RO

Read this register to determine if you turn on Debug features.

This register returns 1 if you turn on Debug features and 0 otherwise

0x0010 USE_CUSTOM_MIN_MAX RO

Read this register to determine if the custom resolution guard bands are on.

This register returns 1 if custom resolution guard bands are on, and 0 otherwise

0x0014 MIN_WIDTH RO Read this register to determine the minimum supported field width
0x0018 MAX_WIDTH RO Read this register to determine the maximum supported field width
0x001C MIN_HEIGHT RO Read this register to determine the minimum supported field height
0x0020 MAX_HEIGHT RO Read this register to determine the maximum supported field height
0x0024 to 0x011F unused
Table 397.  Control and debugging registers

Refer to Image Information Control Packets in the Intel FPGA Streaming Video Protocol Specification, for more details of these registers

Address Register Access 70 Description
Lite Full
0x0120 IMG_INFO_WIDTH RW RO

When you turn on lite, use this register to set the expected width of incoming video fields.

When you turn off lite and turn on Debug features, this register returns the width that the frame cleaner derives from information in the image information control packet.

0x0124 IMG_INFO_HEIGHT RW RO

When you turn on lite, use this register to set the expected height of incoming video fields.

When you turn off lite and turn on Debug features, this register returns the height that the frame cleaner derives from information in the image information control packet.

0x0128 IMG_INFO_INTERLACE - RO When you turn off lite and turn on Debug features, this register returns the interlace nibble that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x012C Reserved - - Reserved
0x0130 IMG_INFO_COLORSPACE - RO When you turn off lite and turn on Debug features, this register returns the color space that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x0134 IMG_INFO_SUBSAMPLING - RO When you turn off lite and turn on Debug features, this register returns the subsampling that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x0138 IMG_INFO_COSITING - RO When you turn off lite and turn on Debug features, this register returns the cositing that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x013C IMG_INFO_FIELD_COUNT - RO When you turn off lite and turn on Debug features, this register returns the field count that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x0138 to 0x013C unused
0x0140 STATUS RO  

Bit 0 : Status bit.

1 = frame cleaner is processing a video field, 0 otherwise. For other bits, see Table 21

0x0144

FIELD_NUM

RO   When you turn off lite and turn on Debug features, reads to this register return the field number value from the most recently received end of field control packet.
0x0148 FIELD_COUNT RO   When you turn on Debug features, reads to this register return the total number of fields received since the debug counts were last reset.
0x014C CLIPPED_FIELD_COUNT RO   When you turn on Debug features, reads to this register return the number of fields that have been clipped to match their expected size since the debug counts were last reset.
0x0150 PADDED_FIELD_COUNT RO   When you turn on Debug features, reads to this register return the number of fields that have been padded to match their expected size since the debug counts were last reset.
0x0154 PREV_FIELD_LINE_COUNT RO   When you turn on Debug features, reads to this register return the number of lines in the most recently completed field.
0x0158 PREV_FIELD_LINE_WIDTH RO   When you turn on Debug features, reads to this register return the number of pixels in the final line of the most recently completed field.
0x015C DEBUG_RESET RW   Write any value to this register to reset all debug counts to 0.

Register Bit Descriptions

Table 398.  PROD_ID
Name Bits Description
Frame cleaner product ID 31:0 This register always returns 0x6AF7_023E.
Table 399.  VER
Name Bits Description
Register map version 7:0 Register map version, returns 0x01.
Unused 15:8 Unused. Returns 0x04
QPDS minor revision 23:16 Updated for each release. For 22.2, returns 0x02
QPDS major revision 31:24 Updated for each release. For 22.2, returns 0x16.
Table 400.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 31:0 Returns 1 if lite mode is on and 0 otherwise
Table 401.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 31:0 Returns 1 if debug features is on and 0 otherwise
Table 402.  USE_CUSTOM_MIN_MAX
Name Bits Description
Use custom min max 31:0 Returns 1 if custom minimum and maximum resolution checks are enabled
Table 403.  MIN_WIDTH
Name Bits Description
Min width 31:0 Minimum output field width
Table 404.  MAX_WIDTH
Name Bits Description
Max width 31:0 Maximum output field width
Table 405.  MIN_HEIGHT
Name Bits Description
Min height 31:0 Minimum output field height

Table 406.  MAX_HEIGHT
Name Bits Description
Max height 31:0 Maximum output field height
Table 407.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

For lite parameterizations, write to this register to set the expected width of the incoming video fields.

For full parameterizations with debug features enabled, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 408.  IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

For lite parameterizations, write to this register to set the expected height of the incoming video fields.

For full parameterizations with debug features enabled, this register reads the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 409.  IMG_INFO_INTERLACE
Name Bits Description
IntlaceNibble bits 3:0

For lite parameterizations, this register has no function.

For full parameterizations with debug features enabled, this register returns the intlaceNibble field from the most recently received image information packet .

unused 31:4 Unused.
Table 410.   IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0

For lite parameterizations, this register has no function.

For full parameterizations with debug features enabled, this register returns the 7 bit CSP field from the most recently received image information packet .

unused 31:7 Unused.
Table 411.  IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0

For lite parameterizations this register has no function.

For full parameterizations with debug features enabled, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 412.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

For lite parameterizations, this register has no function.

For full parameterizations with debug features enabled, this register returns the COSITE field from the most recently received image information packet.

unused 31:2 Unused.
Table 413.  IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0

For lite parameterizations, this register has no function.

For full parameterizations with debug features enabled, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.

unused 31:7 Unused.
Table 414.  STATUS
Name Bits Description
Status bit 0 1 = frame cleaner is processing a video field, 0 otherwise.
Field clipping bit 1 1 = current field is being clipped, 0 otherwise
Field padding bit 2 1 = current field is being padded, 0 otherwise
Previous field clipped 3 1 = previous field was clipped, 0 otherwise
Previous field padded 4 2 = previous field was padded, 0 otherwise
unused 31:5 Unused.
Table 415.  FIELD_NUM
Name Bits Description
Field num 31:0 Field number value taken from the most recently received eof control packet
Table 416.  FIELD_COUNT
Name Bits Description
Field count 31:0 Number of fields received since last debug reset
Table 417.   CLIPPED_FIELD_COUNT
Name Bits Description
Clipped field count 31:0 Number of fields clipped since last debug reset
Table 418.  PADDED_FIELD_COUNT
Name Bits Description
Padded field count 31:0 Number of fields padded since last debug reset
Table 419.   PREV_FIELD_LINE_COUNT
Name Bits Description
Previous field line count 31:0 Number of lines in last completed field
Table 420.  PREV_FIELD_LINE_WIDTH
Name Bits Description
Previous field line width 31:0 Number of pixels in the final line of the previous field
Table 421.  DEBUG_RESET
Name Bits Description
unused 31:0 Unused.
70

You must turn on Debug features to read the values stored in these registers. If Debug features is off, reads to these registers return undefined data. The only exception is the STATUS register, the value of which you can always read.