Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

33.3. Interlacer IP Functional Description

The IP converts input sequences of progressive frames into sequences of alternating F0 and F1 fields. F0 fields contain the even indexed lines from the progressive frame and F1 fields contain the odd indexed lines. Each progressive frame is converted into a single output field, either F0 or F1. The IP has no option to buffer the input frame and output both fields. If the Interlacer IP receives content that is already interlaced, the incoming interlaced fields propagate to the output unaltered.

It may not be appropriate for the interlacer to produce an interlaced sequence according to the original interlaced history for the progressive frames. For example, if frame rate conversion occurs after deinterlacing and before the interlacer, the rate conversion may destroy the original sequence of alternating F0 and F1 fields. You can set a parameter for this feature if you do not turn on Memory-mapped control interface via the register map, or via a register map setting if Memory-mapped control interface is on. This feature is only available when using the full variant of the Intel FPGA Streaming Video protocol as image information packets make it work. Image information packets are not available with the lite variant.

If you do not turn on run-time control of the IP through the register map, the IP converts all progressive input frames to interlaced fields. After any change to the height, width, or interlace identifier specified in the incoming image information packets, the IP resets the sequence of F0 and F1 fields at the output. The Send F1 first parameter sets whether F0 or F1 is sent first after any reset. If you turn on run-time control via the register map, you can select whether the output sequence restarts with an F0 or an F1 field at run time, and the parameter is unused. Run-time control also allows you to turn off interlacing and pass through the progressive frames unaltered. If you turn on Lite mode, you must set the image information values (input frame width, input frame height and input interlace nibble) via the register map. Any edits to these registers cause a reset of the output interlacing sequence. Similarly, changes to these values in the incoming image information packets cause a reset with the full variant of the protocol.

Override of interlace sequence from image information packet

The interlaced nibble field in the Intel FPGA Streaming Video image information packets indicates the progressive or interlaced format for each video field.

Table 522.  Interfaced Nibble Frame Format

The table shows the format specified for each value of this field.

Interlaced nibble Frame format
0 Progressive frame, deinterlaced from an F0 field
1 Progressive frame, deinterlaced from an F1 field
2 Progressive frame
3 Progressive frame
4 Progressive frame, deinterlaced from an F0 field
5 Progressive frame, deinterlaced from an F1 field
6 Progressive frame
7 Progressive frame
8 Interlaced F0 field, paired with the F1 field preceding it
9 Interlaced F0 field, paired with the F1 field following it
10 Interlaced F0 field, pairing unknown
11 Interlaced F0 field, pairing none
12 Interlaced F1 field, paired with the F0 field following it
13 Interlaced F1 field, paired with the F0 field preceding it
14 Interlaced F1 field, pairing unknown
15 Interlaced F1 field, pairing none

By default, the IP passes through fields preceded by image information packets that specify interlaced unaltered. The IP converts progressive frames to an alternating sequence of F0 and F1 fields. However, if a progressive frame has been created as a result of deinterlacing original interlaced content, you may want the interlacer to restore this original interlaced content. Interlace nibble values 0, 1, 4 and 5 allow a system to communicate the original interlaced format of a progressive frame to the interlacer so that this process can be reliably implemented.

If you do not want the interlacer to process any original interlaced history for the progressive frames, the IP does not preserve the original sequence of alternating F0 and F1. For example, if the applies frame fate conversion to progressive frames. You can set a parameter for this feature if you do not turn on Memory-mapped control interface via the register map, or via a register map setting if Memory-mapped control interface is on. This feature is only available when using the full variant of the Intel FPGA Streaming Video protocol as image information packets make it work. Image information packets are not available with the lite variant.