Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

38.3.1. Switch IP Latency

The Switch IP latency depends on clean or crash switches

Clean Switch Latency

When you turn off Crash switching, the IP switch occurs cleanly, with the last packet on each output completed legally, as denoted by tlast.

The switch IP latency for clean switches depends on the complexity of the switch made, the configuration of the switch, the timing of the switch command, the timing on the inputs, and any backpressure experienced on the outputs.

The minimum switch latency (Lclean_switch) is the number of clock cycles from the submitting of a new switch configuration via a write to the COMMIT register, to the start of the first image information packet (full variants) or first line (lite variants) produced at the configured outputs.

Lclean_ switch = Tremaining + 8 + (C ? 6 : 3)*I + 8*O


  • Tremaining = the number of cycles from the write to COMMIT to the end-of-field packet of the current input field (for full variants) or to the TLAST of the current line (lite variants) or to the next TUSER[0] (lite variants with All inputs are uninterrupted on).
  • I = The number of inputs whose state is changing (either consume, enable, disable or destination)
  • O = The number of outputs whose state is changing (either enable, disable, or source)
  • C is 1 with Autoconsume inputs on.

This equation holds in the absence of backpressure and in a fully synchronized system with all switch inputs receiving fields of the same size at the same time, and common host and main clocks.

Latency in a real system is dominated by the timing of the input fields and Lswitch usually only represents a very small percentage of overall switching time.

The fastest switching configurations are lite variants with All inputs are uninterrupted off, as changes occur at line endings, not field endings.

Crash Switch Latency

When you turn on Crash switching, the IP switches occur faster than for clean switching but broken packets may occur at the switch outputs. Crash switch latency is given by Lcrash_switch and switch latency is unaffected by backpressure.

Lcrash_switch <= (Total number of outputs configured)*4 + 4