Stratix V Device Overview

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ID 683258
Date 6/15/2020
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Document Table of Contents
Document Table of Contents x
1. Stratix V Device Overview
1. Stratix V Device Overview x
1.1. Stratix V Family Variants 1.2. Stratix V Features Summary 1.3. Stratix V Family Plan 1.4. Low-Power Serial Transceivers 1.5. PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block) 1.6. External Memory and GPIO 1.7. Adaptive Logic Module 1.8. Clocking 1.9. Fractional PLL 1.10. Embedded Memory 1.11. Variable Precision DSP Block 1.12. Power Management 1.13. Incremental Compilation 1.14. Enhanced Configuration and CvP 1.15. Automatic Single Event Upset Error Detection and Correction 1.16. HardCopy V Devices 1.17. Ordering Information 1.18. Document Revision History
1.14. Enhanced Configuration and CvP x
1.14.1. Partial Reconfiguration
1. Stratix V Device Overview

1.3. Stratix V Family Plan

The following tables list the features of the different Stratix V devices.

The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Altera Product Selector.

Table 2.  Stratix V GT Device Features

Feature

5SGTC5

5SGTC7

Logic Elements (K)

425

622

ALMs

160,400

234,720

Registers (K)

642

939

28.05/12.5-Gbps Transceivers

4/32

4/32

PCIe hard IP Blocks

1

1

Fractional PLLs

28

28

M20K Memory Blocks

2,304

2,560

M20K Memory (MBits)

45

50

Variable Precision Multipliers (18x18)

512

512

Variable Precision Multipliers (27x27)

256

256

DDR3 SDRAM x72 DIMM Interfaces

4

4

User I/Os1, Full-Duplex LVDS, 28.05/12.5-Gbps Transceivers

Package 2 3

5SGTC5

5SGTC7

KF40-F1517 4

(40 mm)

600, 150, 36

600, 150, 36

Table 3.  Stratix V GX Device Features

Features

5SGXA3

5SGXA4

5SGXA5

5SGXA7

5SGXA9

5SGXAB

5SGXB5

5SGXB6

5SGXB9

5SGXBB

Logic Elements (K)

340

420

490

622

840

952

490

597

840

952

ALMs

 128,300 158,500 185,000 234,720 317,000 359,200 185,000 225,400 317,000 359,200

Registers (K)

513

634

740

939

1,268

1,437

740

902

1,268

1,437

14.1-Gbps Transceivers

12, 24, or 36

24 or 36

24, 36, or 48

24, 36, or 48

36 or 48

36 or 48

66

66

66

66

PCIe hard IP Blocks

1 or 2

1 or 2

1, 2, or 4

1, 2, or 4

1, 2, or 4

1, 2, or 4

1 or 4

1 or 4

1 or 4

1 or 4

Fractional PLLs

20 5

24

28

28

28

28

24

24

32

32

M20K Memory Blocks

957

1,900

2,304

2,560

2,640

2,640

2,100

2,660

2,640

2,640

M20K Memory (MBits)

19

37

45

50

52

52

41

52

52

52

Variable Precision Multipliers (18x18)

512

512

512

512

704

704

798

798

704

704

Variable Precision Multipliers (27x27)

256

256

256

256

352

352

399

399

352

352

DDR3 SDRAM x72 DIMM Interfaces 6

6

6

6

6

6

6

4

4

4

4

User I/Os1, Full-Duplex LVDS, 14.1-Gbps Transceivers 

Package 2 3 7 8

5SGXA3

5SGXA4

5SGXA5

5SGXA7

5SGXA9

5SGXAB

5SGXB5

5SGXB6

5SGXB9

5SGXBB

EH29-H780

(33 mm)

360, 90, 12H

—

—

—

—

—

—

—

—

—

HF35-F1152 9

(35 mm)

432, 108, 24

552, 138, 24

552, 138, 24

552, 138, 24

—

—

—

—

—

—

KF35-F1152

(35 mm)

432, 108, 36

432, 108, 36

432, 108, 36

432, 108, 36

—

—

—

—

—

—

KF40-F1517

(40 mm)

KH40-H1517 9

(45 mm)

696, 174, 36

696, 174, 36

696, 174, 36

696, 174, 36

696, 174, 36H

696, 174, 36H

—

—

—

—

NF40-F1517 4

(40 mm)

—

—

600, 150, 48

600, 150, 48

—

—

—

—

—

—

RF40-F1517

(40 mm)

—

—

—

—

—

—

432, 108, 66

432, 108, 66

—

—

RF43-F1760

(42.5 mm)

—

—

—

—

—

—

600, 150, 66

600, 150, 66

—

—

RH43-H1760

(45 mm)

—

—

—

—

—

—

—

—

600, 150, 66H

600, 150, 66H

NF45-F1932 9

(45 mm)

—

—

840, 210, 48

840, 210, 48

840, 210, 48

840, 210, 48

—

—

—

—

Table 4.  Stratix V GS Device Features  

Features

5SGSD3

5SGSD4

5SGSD5

5SGSD6

5SGSD8

Logic Elements (K)

236

360

457

583

695

ALMs

 89,000 135,840 172,600 220,000 262,400

Registers (K)

356

543

690

880

1,050

14.1-Gbps transceivers

12 or 24

12, 24, or 36

24 or 36

36 or 48

36 or 48

PCIe hard IP blocks

1

1

1

1, 2, or 4

1, 2, or 4

Fractional PLLs

20

20 5

24

28

28

M20K Memory Blocks

688

957

2,014

2,320

2,567

M20K Memory (MBits)

13

19

39

45

50

Variable Precision Multipliers (18x18)

1,200

2,088

3,180

3,550

3,926

Variable Precision Multipliers (27x27)

600

1,044

1,590

1,775

1,963

DDR3 SDRAM x72 DIMM Interfaces

2

4

4

6

6

User I/Os1, Full-Duplex LVDS, 14.1-Gbps Transceivers 

Package 2 3 7 8

5SGSD3

5SGSD4

5SGSD5

5SGSD6

5SGSD8

EH29-H780

(33 mm)

360, 90, 12H

360, 90, 12H

—

—

—

HF35-F1152 9

(35 mm)

432, 108, 24

432, 108, 24

552, 138, 24

—

—

KF40-F1517 9

(40 mm)

—

696, 174, 36

696, 174, 36

696, 174, 36

696, 174, 36

NF45-F1932 9

(45 mm)

—

—

—

840, 210, 48

840, 210, 48

Table 5.  Stratix V E Device Features

Features

5SEE9

5SEEB

Logic Elements (K)

840

952

ALMs

317,000

359,200

Registers (K)

1,268

1,437

Fractional PLLs

28

28

M20K Memory Blocks

2,640

2,640

M20K Memory (MBits)

52

52

Variable Precision Multipliers (18x18)

704

704

Variable Precision Multipliers (27x27)

352

352

DDR3 SDRAM x72 DIMM Interfaces

6

6

User I/Os1, Full-Duplex LVDS

Package 2 3 7 8

5SEE9

5SEEB

H40-H1517

(45 mm)

696, 174H

696, 174H

F45-F1932

(45 mm)

840, 210

840, 210

Table 6.  Device Migration List Across All Stratix V Device VariantsAll devices in a specific column allow migration.
Package
EH29- H780

HF35- F1152 10

KF35- F1152

KF40- F1517/ KH40- H1517 11

NF40/ KF40- F1517 12 13

RF40- F1517 H40- H1517 RF43- F1760

NF45- F1932 11

F45- F1932 RH43- H1760
Stratix V GX devices
A3 Yes Yes Yes Yes
A4 Yes Yes Yes
A5 Yes Yes Yes Yes Yes
A7 Yes Yes Yes Yes Yes
A9 Yes Yes
AB Yes Yes
B5 Yes Yes
B6 Yes Yes
B9 Yes
BB Yes
Stratix V GT devices
C5 Yes
C7 Yes
Stratix V GS devices
D3 Yes Yes
D4 Yes Yes Yes
D5 Yes Yes
D6 Yes Yes
D8 Yes Yes
Stratix V E devices
E9 Yes Yes
EB Yes Yes
Note: To verify the pin migration compatibility, use the Pin Migration View window in the Quartus II software Pin Planner.
Related Information
1 The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os.
2 Packages are flipchip ball grid array (1.0-mm pitch).
3 Each package row offers pin migration (common board footprint) for all devices in the row.
4 Migration between select Stratix V GT devices and Stratix V GX devices is available. For more information, refer to Table 6 and to AN 644: Migration Between Stratix V GX and Stratix V GT Devices.
5 The F1517 package contains 24 PLLs. The other packages with this device contain 20 PLLs.
6 These are the maximum number of x72 interfaces available. The actual number of interfaces depends on the device package.
7 LVDS counts are full duplex channels. Each full duplex channel is one transmitter (TX) pair plus one receiver (RX) pair.
8 A superscript H after the number of transceivers indicates that this device is only available in a hybrid package. Hybrid packages are slightly larger than conventional FBGAs. Refer to Altera’s packaging documentation for more information.
9 Migration between select Stratix V GX devices and Stratix V GS devices is available. For more information, refer to Table 6.
10 All devices in this column are in the HF35 package and have twenty-four 14.1-Gbps transceivers.
11 Different devices within this column have small differences in the overall package height. When multiple Stratix V devices with different package heights are placed on a single board, a single-piece heatsink may not cover the devices evenly. Refer to AN 670: Thermal Solutions to Address Height Variation in Stratix V Packages.
12 The 5SGTC5/7 devices in the KF40 package have four 28.05-Gbps transceivers and thirty-two 12.5-Gbps transceivers. Other devices in this column are in the NF40 package and have forty-eight 14.1-Gbps transceivers.
13 For more information, refer to AN 644: Migration Between Stratix V GX and Stratix V GT Devices.
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