Intel® FPGA Package and Thermal Information

Package information includes the ordering code reference, package acronym, leadframe material, lead finish (plating), JEDEC® outline reference, lead coplanarity, weight, moisture sensitivity level, and other special information. The thermal resistance information includes device pin count, package name, and resistance values.

For other devices not listed in the table above, please see the devices packaging datasheet.

Search using package drawing search.

For other related packaging technical information, refer to the following literature.

Package and Thermal Application Notes and White Papers

Title

Application Notes

AN752: Guidelines for Handling Intel® FPGA Wafer level chip scale package
(This application note provides guidelines for handling Intel FPGA's Wafer Level Chip Scale Package (WLCSP) components.)

AN657: Thermal management and mechanical handling for Intel FPGA TCFCBGA devices
(This application note provides guidance on thermal management and mechanical handling of thermal composite flip chip ball-grid array (TCFCBGA) for Intel FPGA devices.)

AN659: Thermal management and mechanical handling for lidless flip chip ball-grid array
(This application note provides guidance on thermal management and mechanical handling of lidless flip chip ball-grid array (FCBGA) for Intel FPGA devices.)

AN 114: Designing with high-density BGA packages for Intel devices

AN 353: SMT board assembly process recommendations

AN 71: Guidelines for handling J-Lead, QFP, BGA, FBGA, and lidless devices

White Papers

Challenges in manufacturing reliable lead-free and RoHS-compliant components