• Added ALM counts and device package sizes to the four device family features tables.
• In the "Stratix V GX Device Features" table, changed the number of DDR3 SDRAM x72 DIMM Interfaces for the 5SGXA3 and 5SGXA4 devices to 6. Also added footnote to this row.
• Deleted listings for 40GBASE-R and 100GBASE-R Ethernet from the "Transceiver PCS Features" table in the "Low-Power Serial Transceivers" section.
• Added YY code to the Optional Suffix category in the "Ordering Information for Stratix V Devices" figure.

Updated "Variable precision DSP blocks" section of the "Features Summary" table to 600 MHz performance.

• Updated GPIOs section of the "Features Summary" table to 1.6 Gbps LVDS.
• Changed clocking speed to 800 MHz in the "Features Summary" and the "Clocking" sections.

• Added link to Altera Product Selector in the "Stratix V Family Plan" section.
• Corrected DDR2 performance from 533 MHz to 400 MHz.
• Updated "Device Migration List Across All Stratix V Device Variants" table.

• Added link to the known document issues in the Knowledge Base.
• Updated backplane support information.
• Added a note about the number of I/Os to each table in the "Stratix V Family Plan" section.
• Updated the "Ordering Information for Stratix V Devices" figure.

December 2012

3.1

• Updated Table 6 and Table 13.
• Updated Figure 2.

June 2012

3.0

• Converted chapter to stand-alone format and removed from the Stratix V handbook.
• Changed title of document to Stratix V Device Overview
• Updated Figure 1.
• Minor text edits.

February 2012

2.3

• Updated Table 1–2, Table 1–3, Table 1–4, and Table 1–5.
• Updated Figure 1–2.
• Updated “Automatic Single Event Upset Error Detection and Correction” on page 18.
• Minor text edits.

December 2011

2.2

Updated Table 1–2 and Table 1–3.

November 2011

2.1

• Changed Stratix V GT transceiver speed from 28 Gbps to 28.05 Gbps.
• Updated Figure 1–2.

November 2011

2.0

• Revised Figure 1–2.
• Updated Table 1–5.
• Minor text edits.

September 2011

1.10

Updated Table 1–2, Table 1–3, and Table 1–4.

September 2011

1.9

• Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, and Table 1–5.
• Updated Figure 1–2.
• Minor text edits.

June 2011

1.8

Changed 800 MHz to 1,066 MHz for DDR3 in Table 1–8 and in text.

May 2011

1.7

• For Stratix V GT devices, changed 14.1 Gbps to 12.5 Gbps.
• Changed Configuration via PCIe to Configuration via Protocol
• Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and Table 1–6.
• Chapter moved to Volume 1.

January 2011

1.6

• Added Stratix V GS information.
• Updated tables listing device features.
• Added device migration information.
• Updated 12.5-Gbps transceivers to 14.1-Gbps transceivers

December 2010

1.5

Updated Table 1-1.

December 2010

1.4

• Updated Table 1-1.
• Updated Figure 1-2.
• Converted to the new template.
• Minor text edits.

July 2010

1.3

Updated Table 1–5

July 2010

1.2

• Updated “Features Summary” on page 1–2
• Updated resource counts in Table 1–1 and Table 1–2
• Removed “Interlaken PCS Hard IP” and “10G Ethernet Hard IP”
• Added “40G and 100G Ethernet Hard IP (Embedded HardCopy Block)” on page 1–7
• Added information about Configuration via PCIe
• Added “Partial Reconfiguration” on page 1–12
• Added “Ordering Information” on page 1–14

May 2010

1.1

Updated part numbers in Table 1–1 and Table 1–2

April 2010

1.0

Initial release