Stratix® V Device Overview

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ID 683258
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® V Device Overview
1. Stratix® V Device Overview x
1.1. Stratix® V Family Variants 1.2. Stratix® V Features Summary 1.3. Stratix® V Family Plan 1.4. Low-Power Serial Transceivers 1.5. PCIe* Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block) 1.6. External Memory and GPIO 1.7. Adaptive Logic Module 1.8. Clocking 1.9. Fractional PLL 1.10. Embedded Memory 1.11. Variable Precision DSP Block 1.12. Power Management 1.13. Incremental Compilation 1.14. Enhanced Configuration and CvP 1.15. Automatic Single Event Upset Error Detection and Correction 1.16. HardCopy V Devices 1.17. Ordering Information 1.18. Revision History for the Stratix® V Device Overview
1.14. Enhanced Configuration and CvP x
1.14.1. Partial Reconfiguration
1. Stratix® V Device Overview

1.10. Embedded Memory

Stratix® V devices contain two types of embedded memory blocks: MLAB (640-bit) and M20K (20-Kbit). MLAB blocks are ideal for wide and shallow memories. M20K blocks are useful for supporting larger memory configurations and include ECC.

Both types of memory blocks operate up to 600 MHz and can be configured to be a single- or dual-port RAM, FIFO, ROM, or shift register. These memory blocks are flexible and support a number of memory configurations, as shown in the following table.

Table 10.  Embedded Memory Block Configuration

MLAB (640 Bits)

M20K (20,480 Bits)

32x20

64x10

512x40

1Kx20

2Kx10

4Kx5

8Kx2

16Kx1

The Quartus II software simplifies design re-use by automatically mapping memory blocks from legacy Stratix® devices into the Stratix® V memory architecture.

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