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1.1. Stratix V Family Variants
1.2. Stratix V Features Summary
1.3. Stratix V Family Plan
1.4. Low-Power Serial Transceivers
1.5. PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)
1.6. External Memory and GPIO
1.7. Adaptive Logic Module
1.8. Clocking
1.9. Fractional PLL
1.10. Embedded Memory
1.11. Variable Precision DSP Block
1.12. Power Management
1.13. Incremental Compilation
1.14. Enhanced Configuration and CvP
1.15. Automatic Single Event Upset Error Detection and Correction
1.16. HardCopy V Devices
1.17. Ordering Information
1.18. Document Revision History
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1.9. Fractional PLL
Stratix V devices contain up to 32 fractional PLLs.
You can use the fractional PLLs to reduce both the number of oscillators required on the board and the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source. In addition, you can use the fractional PLLs for clock network delay compensation, zero delay buffering, and transmitter clocking for transceivers. Fractional PLLs can be individually configured for integer mode or fractional mode with third-order delta-sigma modulation.