1.14.1. Partial Reconfiguration
This capability is required in systems where uptime is critical because partial reconfiguration allows you to make updates or adjust functionality without disrupting services. While lowering power and cost, partial reconfiguration also increases the effective logic density by removing the necessity to place FPGA functions that do not operate simultaneously. Instead, you can store these functions in external memory and load them as required. This capability reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power.
You no longer need to know all the details of the FPGA architecture to perform partial reconfiguration. Altera simplifies the process by extending the power of incremental compilation used in earlier versions of the Quartus II software.
Partial reconfiguration is supported in the following configurations:
- Partial reconfiguration through the FPP x16 I/O interface
- Soft internal core, such as the Nios® II processor.