1.11. Variable Precision DSP Block
Stratix V FPGAs feature the industry’s first variable precision DSP block that you can configure to natively support signal processing with precision ranging from 9x9 to 36x36.
You can independently configure each DSP block at compile time as either a dual 18x18 multiply accumulate or a single 27x27 multiply accumulate. With a dedicated 64-bit cascade bus, you can cascade multiple variable precision DSP blocks to implement even higher precision DSP functions efficiently. The following table describes how variable precision is accommodated within a DSP block or by using multiple blocks.
| Multiplier Size (bits) |
DSP Block Resources |
Expected Usage |
|---|---|---|
| 9x9 |
1/3 of variable precision DSP block |
Low precision fixed point |
| 18x18 |
1/2 of variable precision DSP block |
Medium precision fixed point |
| 27x27 |
1 variable precision DSP block |
High precision fixed or single precision floating point |
| 36x36 |
2 variable precision DSP blocks |
Very high precision fixed point |
Complex multiplication is common in DSP algorithms. One of the most popular applications of complex multipliers is the fast Fourier transform (FFT) algorithm, which increases precision requirements on only one side of the multiplier. The variable precision DSP block is designed to support the FFT algorithm with a proportional increase in DSP resources with precision growth. The following table lists complex multiplication with variable precision DSP blocks.
| Multiplier Size (bits) |
DSP Block Resources |
Expected Usage |
|---|---|---|
| 18x18 |
2 variable precision DSP blocks |
Resource optimized FFTs |
| 18x25 |
3 variable precision DSP blocks |
Accommodate bit growth through FFT stages |
| 18x36 |
4 variable precision DSP blocks |
Highest precision FFT stages |
| 27x27 |
4 variable precision DSP blocks |
Single precision floating point |
For FFT applications with high dynamic range requirements, only the Altera® FFT MegaCore offers an option of single precision floating point implementation, with the resource usage and performance similar to high-precision fixed point implementations.
Other new features include:
- 64-bit accumulator, the largest in the industry
- Hard pre-adder, available in both 18- and 27-bit modes
- Cascaded output adders for efficient systolic FIR filters
- Internal coefficient register banks
- Enhanced independent multiplier operation
- Efficient support for single- and double-precision floating point arithmetic
- Ability to infer all the DSP block modes through HDL code using the Altera Complete Design Suite
The variable precision DSP block is ideal for higher bit precision in high-performance DSP applications. At the same time, the variable precision DSP block can efficiently support the many existing 18-bit DSP applications, such as high definition video processing and remote radio heads. Stratix V FPGAs, with the variable precision DSP block architecture, are the only FPGA family that can efficiently support many different precision levels, up to and including floating point implementations. This flexibility results in increased system performance, reduced power consumption, and reduced architecture constraints for system algorithm designers.