Stratix V Device Overview

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ID 683258
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Stratix V Device Overview
1. Stratix V Device Overview x
1.1. Stratix V Family Variants 1.2. Stratix V Features Summary 1.3. Stratix V Family Plan 1.4. Low-Power Serial Transceivers 1.5. PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block) 1.6. External Memory and GPIO 1.7. Adaptive Logic Module 1.8. Clocking 1.9. Fractional PLL 1.10. Embedded Memory 1.11. Variable Precision DSP Block 1.12. Power Management 1.13. Incremental Compilation 1.14. Enhanced Configuration and CvP 1.15. Automatic Single Event Upset Error Detection and Correction 1.16. HardCopy V Devices 1.17. Ordering Information 1.18. Document Revision History
1.14. Enhanced Configuration and CvP x
1.14.1. Partial Reconfiguration
1. Stratix V Device Overview

1.2. Stratix V Features Summary

Table 1.  Summary of Features for Stratix V Devices
Feature Description
Technology
  • 28-nm TSMC process technology
  • 0.85-V or 0.9-V core voltage
Low-power serial transceivers
  • 28.05-Gbps transceivers on Stratix V GT devices
  • Electronic dispersion compensation (EDC) for XFP, SFP+, QSFP, CFP optical module support
  • Adaptive linear and decision feedback equalization
  • Transmitter pre-emphasis and de-emphasis
  • Dynamic reconfiguration of individual channels
  • On-chip instrumentation (EyeQ non-intrusive data eye monitoring)
Backplane capability
  • 600-Megabits per second (Mbps) to 12.5-Gbps data rate capability
General-purpose I/Os (GPIOs)
  • 1.6-Gbps LVDS
  • 1,066-MHz external memory interface
  • On-chip termination (OCT)
  • 1.2-V to 3.3-V interfacing for all Stratix V devices
Embedded HardCopy Block
  • PCIe Gen3, Gen2, and Gen1 complete protocol stack, x1/x2/x4/x8 end point and root port
Embedded transceiver hard IP
  • Interlaken physical coding sublayer (PCS)
  • Gigabit Ethernet (GbE) and XAUI PCS
  • 10G Ethernet PCS
  • Serial RapidIO® (SRIO) PCS
  • Common Public Radio Interface (CPRI) PCS
  • Gigabit Passive Optical Networking (GPON) PCS
Power management
  • Programmable Power Technology
  • Quartus II integrated PowerPlay Power Analysis
High-performance core fabric
  • Enhanced ALM with four registers
  • Improved routing architecture reduces congestion and improves compile times
Embedded memory blocks
  • M20K: 20-Kbit with hard error correction code (ECC)
  • MLAB: 640-bit
Variable precision DSP blocks
  • Up to 600 MHz performance
  • Natively support signal processing with precision ranging from 9x9 up to 54x54
  • New native 27x27 multiply mode
  • 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
  • Embedded internal coefficient memory
  • Pre-adder/subtractor improves efficiency
  • Increased number of outputs allows more independent multipliers
Fractional PLLs
  • Fractional mode with third-order delta-sigma modulation
  • Integer mode
  • Precision clock synthesis, clock delay compensation, and zero delay buffer (ZDB)
Clock networks
  • 800-MHz fabric clocking
  • Global, quadrant, and peripheral clock networks
  • Unused clock networks can be powered down to reduce dynamic power
Device configuration
  • Serial and parallel flash interface
  • Enhanced advanced encryption standard (AES) design security features
  • Tamper protection
  • Partial and dynamic reconfiguration
  • Configuration via Protocol (CvP)
High-performance packaging
  • Multiple device densities with identical package footprints enables seamless migration between different FPGA densities
  • FBGA packaging with on-package decoupling capacitors
  • Lead and RoHS-compliant lead-free options
HardCopy V migration —
Level Two Title