1.4. Low-Power Serial Transceivers
Stratix V FPGAs deliver the industry’s most flexible transceivers with the highest bandwidth from 600 Mbps to 28.05 Gbps, low bit error ratio (BER), and low power. Stratix V transceivers have many enhancements to improve flexibility and robustness. These enhancements include robust analog receiver clock and data recovery (CDR), advanced pre-emphasis, and equalization. In addition, each channel provides full featured embedded PCS hard IP to simplify the design, lower the power, and save valuable core resources.
Stratix V transceivers are compliant with a wide range of standard protocols and data rates and are equipped with a variety of signal conditioning features to support backplane, optical module, and chip-to-chip applications.
Stratix V transceivers are located on the left and right sides of the device, as shown in the figure below. The transceivers are isolated from the rest of the chip to prevent core and I/O noise from coupling into the transceivers, thereby ensuring optimal signal integrity. The transceiver channels consist of the physical medium attachment (PMA), PCS, and high-speed clock networks. You can also configure unused transceiver PMA channels as additional transmitter PLLs.
Figure 1. Stratix V GT, GX, and GS Device Chip View
This figure represents one variant of a Stratix V device with transceivers. Other variants may have a different floorplan than the one shown here.
The following table lists the PMA features for the Stratix V transceivers.
| Feature |
Capability |
|---|---|
| Chip-to-chip support |
28.05 Gbps and 12.5 Gbps (Stratix V GT devices) and 14.1 Gbps (Stratix V GX and GS devices) |
| Backplane support |
12.5 Gbps (Stratix V GX, GS, and GT devices) |
| Cable driving support |
PCIe cable and eSATA applications |
| Optical module support with EDC |
10G Form-factor Pluggable (XFP), Small Form-factor Pluggable (SFP+), Quad Small Form-factor Pluggable (QSFP), CXP, 100G Pluggable (CFP), 100G Form-factor Pluggable |
| Continuous Time Linear Equalization (CTLE) |
Receiver 4-stage linear equalization to support high-attenuation channels |
| Decision Feedback Equalization (DFE) |
Receiver 5-tap digital equalizer to minimize losses and crosstalk |
| Adaptive equalization (AEQ) |
Adaptive engine to automatically adjust equalization to compensate for changes over time |
| PLL-based clock recovery |
Superior jitter tolerance versus phase interpolation techniques |
| Programmable deserialization and word alignment |
Flexible deserialization width and configurable word alignment patterns |
| Transmitter equalization (pre-emphasis) |
Transmitter driver 4-tap pre-emphasis and de-emphasis for protocol compliance under lossy conditions |
| Ring and LC oscillator transmitter PLLs |
Choice of transmitter PLLs per channel, optimized for specific protocols and applications |
| On-chip instrumentation (EyeQ data-eye monitor) |
Allows non-intrusive on-chip monitoring of both width and height of the data eye |
| Dynamic reconfiguration |
Allows reconfiguration of single channels without affecting operation of other channels |
| Protocol support |
Compliance with over 50 industry standard protocols in the range of 600 Mbps to 28.05 Gbps |
The Stratix V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, 40-, 64-, or 66-bit interface, depending on the transceiver data rate and protocol. Stratix V devices contain PCS hard IP to support PCIe Gen3, Gen2, Gen1, Interlaken, 10GE, XAUI, GbE, SRIO, CPRI, and GPON protocols. All other standard and proprietary protocols are supported through the transceiver PCS hard IP. The following table lists the transceiver PCS features.
| Protocol |
Data Rates (Gbps) |
Transmitter Data Path |
Receiver Data Path |
|---|---|---|---|
| Custom PHY |
0.6 to 8.5 |
Phase compensation FIFO, byte serializer, 8B/10B encoder, bit-slip, and channel bonding |
Word aligner, de-skew FIFO, rate match FIFO, 8B/10B decoder, byte deserializer, and byte ordering |
| Custom 10G PHY |
9.98 to 14.1 |
TX FIFO, gear box, and bit-slip |
RX FIFO and gear box |
| x1, x4, x8 PCIe Gen1 and Gen2 |
2.5 and 5.0 |
Same as custom PHY plus PIPE 2.0 interface to core logic |
Same as custom PHY plus PIPE 2.0 interface to core logic |
| x1, x4, x8 PCIe Gen3 |
8 |
Phase compensation FIFO, encoder, scrambler, gear box, and bit-slip |
Block synchronization, rate match FIFO, decoder, de-scrambler, and phase compensation FIFO |
| 10G Ethernet |
10.3125 |
TX FIFO, 64/66 encoder, scrambler, and gear box |
RX FIFO, 64/66 decoder, de-scrambler, block synchronization, and gear box |
| Interlaken |
4.9 to 14.1 |
TX FIFO, frame generator, CRC-32 generator, scrambler, disparity generator, and gear box |
RX FIFO, frame generator, CRC-32 checker, frame decoder, descrambler, disparity checker, block synchronization, and gearbox |
| OTN 40 and 100 |
(4 +1) x 11.3 |
TX FIFO, channel bonding, and byte serializer |
RX FIFO, lane deskew, and byte de-serializer |
| (10 +1) x 11.3 |
|||
| GbE |
1.25 |
Same as custom PHY plus GbE state machine |
Same as custom PHY plus GbE state machine |
| XAUI |
3.125 to 4.25 |
Same as custom PHY plus XAUI state machine for bonding four channels |
Same as custom PHY plus XAUI state machine for re-aligning four channels |
| SRIO |
1.25 to 6.25 |
Same as custom PHY plus SRIO V2.1 compliant x2 and x4 channel bonding |
Same as custom PHY plus SRIO V2.1compliant x2 and x4 deskew state machine |
| CPRI |
0.6144 to 9.83 |
Same as custom PHY plus TX deterministic latency |
Same as custom PHY plus RX deterministic latency |
| GPON |
1.25, 2.5, and 10 |
Same as custom PHY |
Same as custom PHY |