Stratix V Device Overview

ID 683258
Date 6/15/2020
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1.8. Clocking

The Stratix V device core clock network is designed to support 800-MHz fabric operations and 1,066-MHz and 1,600-Mbps external memory interfaces.

The clock network architecture is based on Altera’s proven global, quadrant, and peripheral clock structure, which is supported by dedicated clock input pins and fractional clock synthesis PLLs. The Quartus II software identifies all unused sections of the clock network and powers them down, which reduces power consumption.