Stratix V Device Overview

ID 683258
Date 6/15/2020
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1.6. External Memory and GPIO

Each Stratix V I/O block has a hard FIFO that improves the resynchronization margin as data is transferred from the external memory to the FPGA.

The hard FIFO also lowers PHY latency, resulting in higher random access performance. GPIOs include on-chip dynamic termination to reduce the number of external components and minimize reflections. On-package decoupling capacitors suppress noise on the power lines, which reduce noise coupling into the I/Os. Memory banks are isolated to prevent core noise from coupling to the output, thus reducing jitter and providing optimal signal integrity.

The external memory interface block uses advanced calibration algorithms to compensate for process, voltage and temperature (PVT) variations in the FPGA and external memory components. The advanced algorithms ensure maximum bandwidth and a robust timing margin across all conditions. Stratix V devices deliver a complete memory solution with the High Performance Memory Controller II (HPMC II) and UniPHY MegaCore® IP that simplifies a design for today’s advanced memory modules. The following table lists external memory interface block performance.

Table 9.  External Memory Interface PerformanceThe specifications listed in this table are performance targets. For a current achievable performance, use the External Memory Interface Spec Estimator.

Interface

Performance (MHz)

DDR3

933

DDR2

400

QDR II

350

QDR II+

550

RLDRAM II

533

RLDRAM III

800