1.1. Stratix® V Family Variants
1.2. Stratix® V Features Summary
1.3. Stratix® V Family Plan
1.4. Low-Power Serial Transceivers
1.5. PCIe* Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)
1.6. External Memory and GPIO
1.7. Adaptive Logic Module
1.8. Clocking
1.9. Fractional PLL
1.10. Embedded Memory
1.11. Variable Precision DSP Block
1.12. Power Management
1.13. Incremental Compilation
1.14. Enhanced Configuration and CvP
1.15. Automatic Single Event Upset Error Detection and Correction
1.16. HardCopy V Devices
1.17. Ordering Information
1.18. Revision History for the Stratix® V Device Overview
1.17. Ordering Information
This section describes ordering information for Stratix® V GT, GX, GS, and E devices.
The following figure shows the ordering codes for the Stratix® V devices.
Figure 2. Ordering Information for Stratix® V Devices