Enhanced Configuration (EPC) Devices Datasheet

ID 683253
Date 5/04/2016
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1.9. Timing Information

Figure 7. Configuration Timing Waveform Using an EPC Device
Table 13.   EPC Device Configuration Timing Parameters
Symbol Parameter Condition Min Typ Max Unit
fDCLK DCLK frequency 40% duty cycle 66.7 MHz
tDCLK DCLK period 15 ns
tHC DCLK duty cycle high time 40% duty cycle 6 ns
tLC DCLK duty cycle low time 40% duty cycle 6 ns
tCE OE to first DCLK delay 40 ns
tOE OE to first DATA available 40 ns
tOH DCLK rising edge to DATA change 6 ns
tCF 7 OE assert to DCLK disable delay 277 ns
tDF 7 OE assert to DATA disable delay 277 ns
tRE 8 DCLK rising edge to OE 60 ns
tLOE OE assert time to assure reset 60 ns
fECLK 9 EXCLK input frequency 40% duty cycle 100 MHz
6 To calculate tOH, use the following equation: tOH = 0.5 (DCLK period) - 2.5 ns.
7 This parameter is used for CRC error detection by the FPGA.
8 This parameter is used for CONF_DONE error detection by the EPC device.
9 The FPGA VCCINT ramp time should be less than 1ms for 2-ms POR and it should be less than 70 ms for 100-ms POR.